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AM69AX 数据表(PDF) 86 Page - Texas Instruments

部件名 AM69AX
功能描述  AM69Ax Processors, Silicon Revision 1.0
PDF  299 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

AM69AX 数据表(HTML) 86 Page - Texas Instruments

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Table 6-4. MCU_ADC1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALY PIN [4]
MCU_ADC1_REFN
A
ADC Reference (Negative)
W35
MCU_ADC1_REFP
A
ADC Reference (Positive)
AA35
MCU_ADC1_AIN0
A
ADC Input 0
Y38
MCU_ADC1_AIN1
A
ADC Input 1
Y34
MCU_ADC1_AIN2
A
ADC Input 2
V34
MCU_ADC1_AIN3
A
ADC Input 3
W37
MCU_ADC1_AIN4
A
ADC Input 4
AA37
MCU_ADC1_AIN5
A
ADC Input 5
W33
MCU_ADC1_AIN6
A
ADC Input 6
U33
MCU_ADC1_AIN7
A
ADC Input 7
Y36
6.3.2 DDRSS
6.3.2.1 MAIN Domain
Table 6-5. DDRSS0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALY PIN [4]
DDR0_CKN
IO
DDRSS Differential Clock (negative)
AB2
DDR0_CKP
IO
DDRSS Differential Clock (positive)
AC1
DDR0_RESETn
IO
DDRSS Reset
AD5
DDR0_RET
I
DDR Retention Enable
AC8
DDR0_CA0
IO
DDRSS Command Address
AD2
DDR0_CA1
IO
DDRSS Command Address
AC5
DDR0_CA2
IO
DDRSS Command Address
AB4
DDR0_CA3
IO
DDRSS Command Address
AC4
DDR0_CA4
IO
DDRSS Command Address
AB3
DDR0_CA5
IO
DDRSS Command Address
AC3
DDR0_CAL0 (1)
A
IO Pad Calibration Resistor
AE8
DDR0_CKE0
IO
DDRSS Clock Enable
AB6
DDR0_CKE1
IO
DDRSS Clock Enable
AD3
DDR0_CSn0_0
IO
DDRSS Chip Select
AD7
DDR0_CSn0_1
IO
DDRSS Chip Select
AC7
DDR0_CSn1_0
IO
DDRSS Chip Select
AB7
DDR0_CSn1_1
IO
DDRSS Chip Select
AD6
DDR0_DM0
IO
DDRSS Data Mask
V3
DDR0_DM1
IO
DDRSS Data Mask
AA4
DDR0_DM2
IO
DDRSS Data Mask
AG2
DDR0_DM3
IO
DDRSS Data Mask
AJ5
DDR0_DQ0
IO
DDRSS Data
U2
DDR0_DQ1
IO
DDRSS Data
U4
DDR0_DQ2
IO
DDRSS Data
W6
DDR0_DQ3
IO
DDRSS Data
W5
DDR0_DQ4
IO
DDRSS Data
V4
DDR0_DQ5
IO
DDRSS Data
V7
DDR0_DQ6
IO
DDRSS Data
U5
DDR0_DQ7
IO
DDRSS Data
V6
DDR0_DQ8
IO
DDRSS Data
Y2
AM69A
SPRSP92 – FEBRUARY 2023
www.ti.com
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Product Folder Links: AM69A



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