AM69AX datasheet(138/299 Pages) TI

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7.5 Operating Performance Points

This section describes the operating conditions of the device. This section also contains the description of each

Operating Performance Point (OPP) for processor clocks and device core clocks.

Table 7-1 describes the maximum supported frequency per speed grade for the device.

Table 7-1. Speed Grade Maximum Frequency

DEVICE

MAXIMUM FREQUENCY (MHz)

A72SS0

C71SS0

R5FSS0/1

MCU_

R5SS0

GPU

CBASS0

VPAC

VENCDEC

DMSC

LPDDR4

AM69Ax...T

2000

1000

800

500

720

550 (960 or

480MP/s)(2)

333

4266 MT/s(1)

(1)

Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.

TI strongly recommends all designs to follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing, spacing, vias/backdrill,

PCB material, etc.) in order to achieve the full specified clock frequency. Refer to the Jacinto 7 LPDDR Board Design and Layout

Guidelines for details

(2)

Refer to the Device Comparison table to determine specific part numbers that include 1 × VENCDEC module (480 MP/s) or 2

×VENCDEC modules (960 MP/s).

AM69A

SPRSP92 – FEBRUARY 2023

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