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7.10.2.2 Combined MCU and Main Domains Power- Up Sequencing

Section 7.10.2.2 describes the primary power-up sequencing when similar MCU and Main voltage domains

are combined into common power rails. Combining MCU and Main voltage domains simplifies PDN design

by reducing total number of power rails and sources while making MCU and Main processor sub-systems

operational dependent on common power rails.

J7VCL_ELCH_01

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,

VDDSHV0, VDDSHV2, VDDSHV5 ) , VDDA_3P3_USB

(D) (B)

(E)

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,

VDDSHV0, VDDSHV2, VDDSHV5 ) ,VDDS_MMC0

(D) (C)

VDD_CPU

VDD_MCU , VDD_MCU_WAKE1, VDD_CORE,

(I)

VDD_WAKE0, VDDA_0P8_SERDES,

VDDA_0P8_SERDES_C, VDDA_0P8_USB,

VDDAR_CORE, VDDAR_CPU, VDDAR_MCU

(I)

MCU_PORz

(J)(K)

OSC1_XI, OSC1_XO

(optional)

WKUP_LFOSC0_XI, WKUP_LFOSC0_XO

(optional)

WKUP_OSC0_XI, WKUP_OSC0_XO

VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C,

VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0

(H)

MCU_BOOTMODE[9:0], BOOTMODE[7:0]

(J)

Valid Configuration

(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,

VDDA_POR_WKUP, VDDA_WKUP, VDDA_OSC1,

VDDA_PLLGRP8, VDDA_PLLGRP6,VDDA_PLLGRP4,

VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1)

(F)

(VDDA_1P8_SERDES, VDDA_1P8_USB)

(G)

PORz

(J)(K)

Time stamp markers:

•

T0 – 3.3V voltages start ramp-up to VOPR MIN. (0 ms)

•

T1 – 1.8-V voltages start ramp-up to VOPR MIN. (2 ms)

•

T2 – Low voltage core supplies start ramp-up to VOPR MIN. (3 ms)

•

T3 – Low voltage RAM array voltages start ramp-up to VOPR MIN. (4 ms)

•

T4 – OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (13 ms)

Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to support 3.3V digital interfaces. A

few supplies could have varying start times between T0 to T1 due to PDN designs using different power resources with varying turn-on

& ramp-up time delays.

Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.

When eMMC memories are used, Main 1.8-V supplies could have a ramp-up aligned to T3 due to PDN designs grouping supplies with

VDD_MMC0.

VDDSHV5 supports MMC1 signaling for SD memory cards. If compliant high-speed SD card operation is needed, then an independent,

dual voltage (3.3 V/1.8 V) power source and rail are required. The start of ramp-up to 3.3 V will be same as other 3.3-V domains as

shown. If SD card is not needed or standard data rates with fixed 3.3 V operation is acceptable, then domain can be grouped with digital

IO 3.3-V power rail. If a SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO 1.8-V power rail.

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AM69A

SPRSP92 – FEBRUARY 2023

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