pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops that conduct an

alternating current must outline an area as small as possible, as this area is proportional to the energy radiated.

Sensitive nodes like FB must be connected with short wires and not nearby high dv/dt signals (for example SW).

Because they carry information about the output voltage, they must be connected as close as possible to the

actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R1

and R2, must be kept close to the IC and connect directly to those pins and the system ground plane.

The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help spread the heat

into the pcb.

The recommended layout is implemented on the EVM and shown in the TPS62810EVM-015 Evaluation Module

user's guide.

10.5.2 Layout Example

GND

VIN

GND

VOUT

Figure 10-63. Example Layout

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TPS62810-Q1, TPS62811-Q1, TPS62812-Q1, TPS62813-Q1

SLVSDU1J – AUGUST 2018 – REVISED MARCH 2023

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