9 Detailed Description

9.1 Overview

The TPS6281x-Q1 synchronous switch mode DC/DC converters are based on a peak current mode control

topology. The control loop is internally compensated. To optimize the bandwidth of the control loop to the

wide range of output capacitance that can be used with TPS6281x-Q1, one of three internal compensation

settings can be selected. See Section 9.3.2. The compensation setting is selected either by a resistor from

COMP/FSET to GND, or by the logic state of this pin. The regulation network achieves fast and stable operation

with small external components and low ESR ceramic output capacitors. The device can be operated without

a feedforward capacitor on the output voltage divider, however, using a typically 10-pF feedforward capacitor

improves transient response.

The devices support forced fixed frequency PWM operation with the MODE pin tied to a logic high level. The

frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN, or in a

range of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can

be synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin

with no need for additional passive components. External synchronization is only possible if a resistor from

COMP/FSET to GND is used. If COMP/FSET is directly tied to GND or VIN, the TPS6281x-Q1 cannot be

synchronized externally. An internal PLL allows to change from internal clock to external clock during operation.

The synchronization to the external clock is done on a falling edge of the clock applied at MODE to the

rising edge on the SW pin. This allows a roughly 180° phase shift when the SW pin is used to generate

the synchronization signal for a second converter. When the MODE pin is set to a logic low level, the device

operates in power save mode (PFM) at low output current and automatically transfers to fixed frequency PWM

mode at higher output current. In PFM mode, the switching frequency decreases linearly based on the load to

sustain high efficiency down to very low output current.

9.2 Functional Block Diagram

_

+

+

-

GND

FB

SW

VIN

EN

Oscillator

Gate Drive and Control

Device

Control

PG

Thermal

Shutdown

Bias

Regulator

gm

Ipeak

Izero

Bandgap

SS/TR

COMP/FSET

MODE

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TPS62810-Q1, TPS62811-Q1, TPS62812-Q1, TPS62813-Q1

SLVSDU1J – AUGUST 2018 – REVISED MARCH 2023

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Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1