clock in a frequency range from 1.8 MHz to 4 MHz for external synchronization. Similar to COMP/FSET, the

specifications for the minimum on-time and minimum off-time have to be taken into account when setting

the external frequency. For use with external synchronization on the MODE/SYNC pin, the internal switching

frequency must be set by RCF to a similar value than the externally applied clock. This ensures a fast settling

to the external clock and, if the external clock fails, the switching frequency stays in the same range and the

compensation settings are still valid. When there is no resistor from COMP/FSET to GND but the pin is pulled

high or low, external synchronization is not possible.

9.3.4 Spread Spectrum Clocking (SSC)

For device versions with SSC enabled, the switching frequency is randomly changed in PWM mode when the

internal clock is used. The frequency variation is typically between the nominal switching frequency and up to

288 kHz above the nominal switching frequency. When the device is externally synchronized by applying a clock

signal to the MODE/SYNC pin, the TPS6281x-Q1 follows the external clock and the internal spread spectrum

block is turned off. SSC is also disabled during soft start.

9.3.5 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both

the power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the

input voltage trips below the threshold for a falling supply voltage.

9.3.6 Power Good Output (PG)

Power good is an open-drain output driven by a window comparator. PG is held low when the device is disabled,

in undervoltage lockout, and in thermal shutdown. When the output voltage is in regulation hence, within the

window defined in the electrical characteristics, the output is high impedance.

Table 9-3. PG Status

EN

DEVICE STATUS

PG STATE

X

VIN < 2 V

undefined

low

VIN ≥ 2 V

low

high

2 V ≤ VIN ≤ UVLO OR in thermal shutdown OR VOUT not in regulation

low

high

VOUT in regulation

high impedance

9.3.7 Thermal Shutdown

The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 170°C

(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and

PG goes low. When TJ decreases by the hysteresis amount of typically 15°C, the converter resumes normal

operation, beginning with soft start. During a PFM pause, the thermal shutdown is not active. After a PFM pause,

the device needs up to 9 µs to detect a too high junction temperature. If the PFM burst is shorter than this delay,

the device does not detect a too high junction temperature.

9.4 Device Functional Modes

9.4.1 Pulse Width Modulation (PWM) Operation

TPS6281x-Q1 has two operating modes: Forced PWM mode (discussed in this section) and PWM/PFM

(discussed in Section 9.4.2).

With the MODE/SYNC pin set to high, the TPS6281x-Q1 operates with pulse width modulation in continuous

conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP pin to GND or

by an external clock signal applied to the MODE/SYNC pin. With an external clock is applied to MODE/SYNC,

the TPS6281x-Q1 follows the frequency applied to the pin. To maintain regulation, the frequency must be in a

range the TPS6281x-Q1 can operate at, taking the minimum on-time into account.

9.4.2 Power Save Mode Operation (PWM/PFM)

When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long

as the peak inductor current is above the PFM threshold of about 1.2 A. When the peak inductor current

TPS62810-Q1, TPS62811-Q1, TPS62812-Q1, TPS62813-Q1

SLVSDU1J – AUGUST 2018 – REVISED MARCH 2023

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