82C85

FN2976 Rev.0.00

Page 3 of 21

March 1997

Functional Block Diagram

RESET

16

O

RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its timing

characteristics are determined by RES. RESET is guaranteed to be HIGH for a minimum of 16 CLK puls-

es after the rising edge of RES.

CSYNC

1

I

CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C85 and

82C84A to be synchronized to provide multiple in-phase clock signals When CSYNC is HIGH, the inter-

nal counters are reset and force CLK, CLK50 and PCLK into a HIGH state. When CSYNC is LOW, the

internal counters are allowed to count and the CLK, CLK50 and PCLK outputs are active. CSYNC must

be externally synchronized to EFI.

AEN1

AEN2

3

7

I

I

ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready Sig-

nal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are

useful in system configurations which permit the processor to access two Multi-Master System Buses.

RDY1

RDY2

4

6

I

I

BUS READY: (Transfer Complete). RDY is an active HIGH signal which is an indication from a device

located on the system data bus that data has been received, or is available RDY1 is qualified by AEN1

while RDY2 is qualified by AEN2.

ASYNC

21

I

READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of

the READY logic. When ASYNC is LOW, two stages of READY synchronization are provided. When

ASYNC is left open or HIGH a single stage of READY synchronization is provided.

READY

5

O

READY: READY is an active HIGH signal which is the synchronized RDY signal input.

GND

9

I

Ground

VCC

24

I

VCC: is the +5V power supply pin. A 0.1mF capacitor between VCC and GND is recommended.

Pin Descriptions (Continued)

SYMBOL

DIP PIN

NUMBER

TYPE

DESCRIPTION

STOP LOGIC

SYNC

LOGIC

PERIPHERAL

CLOCK

(DIVIDE BY 6)

READY

SYNC

OSCILLATOR

READY

SELECT

SPEED SELECT

DIV 256 OR DIV 1

RESTART

LOGIC

CLOCK

(DIVIDE

LOGIC

BY 3)

RESET PULSE

CONDITIONING

LOGIC

RESET

CLK

CLK50

PCLK

OSC

READY

(16)

(8)

(10)

(2)

(18)

(5)

(17)

(1)

(12)

(19)

(23)

(21)

(11)

(20)

(22)

(15)

(14)

(13)

(4)

(3)

(7)

(6)

RES

START

CSYNC

SLO/FST

F/C

EFI

X2

X1

S2/STOP

S1

S0

RDY1

AEN1

AEN2

RDY2

ASYNC

RESTART

SYNC

MASTER

SELECTED

OSC

HALT

VCC (24)

GND (9)

OSC

EXTERNAL

FREQ.

SELECT