82C85

FN2976 Rev.0.00

Page 4 of 21

March 1997

Functional Description

The 82C85 Static Clock Controller/Generator provides simple

and complete control static CMOS system operating modes.

The 82C85 supports full speed, slow, stop-clock and stop-

oscillator operation. While it is directly compatible with the

Intersil 80C86 and 80C88 CMOS 16-bit static microprocessors,

the 82C85 can also be used for general purpose system clock

control.

The 82C85 pinout is a superset of the 82C84A Clock Genera-

tor/Driver. 82C85 pins 1-9, 16-24 are compatible with 82C84A

pins 1-9, 10-18 respectively. An 82C84A can be placed in the

upper 18 pins of an 82C85 socket and it will operate correctly

(without the ability to control the clock and oscillator operation.)

This allows dual design for simple system upgrades. The

82C85 will also emulate an 82C84A when pins 11-15 on the

82C85 are tied to VCC.

For static systems designs, separate signals are provided on

the 82C85 for stop and start control of the crystal oscillator and

clock outputs. A single control line determines 82C85 fast

(crystal/EFI frequency divided by 3) or slow (crystal/EFI fre-

quency divided by 768) mode operation. The 82C85 also con-

tains a crystal controlled oscillator, clock generation logic,

complete “Ready” synchronization and reset logic.

Automatic 80C86/88 software HALT instruction decode logic is

present to ease the design of software-based clock control sys-

tems and provide complete software control of STOP mode

operation. Restart logic insures valid clock start-up and com-

plete synchronization of CLK, CLK50 and PCLK.

Static Operating Modes

In static CMOS system design, there are four basic operating

modes. The 82C85 Static Clock Controller supports each of

them. These modes are: FAST, SLOW, STOP-CLOCK and

STOP-OSCILLATOR. Each has distinct power and perfor-

mance characteristics which can be matched to the needs of a

particular system at a specific time (See Table 1).

Keep in mind that a single system may require all of these oper-

ating modes at one time or another during normal operation. A

design need not be limited to a single operating mode or a spe-

cific combination of modes. The appropriate operating mode can

be matched to the power-performance level needed at a specific

time or in a particular circumstance.

Reset Logic

The 82C85 reset logic provides a Schmitt trigger input (RES)

and a synchronizing flip-flop to generate the reset timing. The

reset signal is synchronized to the falling edge of CLK. A sim-

ple RC network can be used to provide power-on reset by uti-

lizing this function of the 82C85.

When in the crystal oscillator (F/C = LOW) or the EFI (F/C =

HIGH) mode, a LOW state on the RES input will set the

RESET output to the HIGH state. It will also restart the oscilla-

tor circuit if it is in the idle state. The RESET output is guaran-

teed to stay in the HIGH state for a minimum of 16 CLK cycles

after a low-to-high transition of the RES input.

An oscillator restart count sequence will not be disturbed by

RESET if this count is already in progress. After the restart

counter expires, the RESET output will stay HIGH at least for 16

periods of CLK before going LOW. RESET can be kept high

beyond this time by a continuing low input on the RES input.

If F/C is low (crystal oscillator mode), a low state on RES starts

the crystal oscillator circuit. The stopped outputs remain inac-

tive, until the oscillator signal amplitude reaches the X1

Schmitt trigger input threshold voltage and 8192 cycles of the

crystal oscillator output are counted by an internal counter.

After this count is complete, the stopped outputs (CLK, CLK50,

PCLK, and OSC) start cleanly with the proper phase relation-

ships.

This 8192 count requirement insures that the CLK, CLK50 and

PCLK outputs will meet minimum clock requirements and will

not be affected by unstable oscillator characteristics which may

exist during the oscillator start-up sequence. This sequence is

also followed when a START command is issued while the

82C85 oscillator is stopped.

Oscillator/Clock Start Control

Once the oscillator is stopped (or committed to stop) or at power-

on, the restart sequence is initiated by a HIGH state on START or

LOW state on RES. If F/C is HIGH, then restart occurs immediately

after the START or RES input is synchronized internally. This

insures that stopped outputs (CLK, PCLK, OSC and CLK50) start

cleanly with the proper phase relationship.

If F/C is low (crystal oscillator mode), a HIGH state on the

START input or a low state on RES causes the crystal oscilla-

tor to be restarted. The stopped outputs remain stopped,

TABLE 1. STATIC SYSTEM OPERATING MODE CHARACTERISTICS

OPERATING

MODE

DESCRIPTION

POWER LEVEL

PERFORMANCE

Stop-Oscillator

All system clocks and main clock oscillator are stopped

Maximum Savings

Slowest response due to oscillator

restart time

Stop-Clock

System CPU and peripherals clocks stop but main clock

oscillator continues to run at rated frequency

Reduced System

Power

Fast restart-no oscillator restart time

Slow

System CPU clocks are slowed while peripheral clock

and main clock oscillator run at rated frequency

Power Dissipation

Slightly Higher Than

Stop-Clock

Continuous operation at low frequency

Fast

All clocks and oscillators run at rated frequency

Highest Power

Fastest response