82C85

FN2976 Rev.0.00

Page 9 of 21

March 1997

Clock Generator

The clock generator consists of two synchronous divide-by-

three counters with special clear inputs that inhibit the count-

ing. One counter generates a 33% duty cycle waveform (CLK)

and the other generates a 50% duty cycle waveform (CLK50).

These two counters are negative-edge synchronized, with the

low-going transitions of both waveforms occurring on the same

oscillator transition. The CLK and CLK50 output frequencies

are one-third of the base input frequency when SLO/FST is

high and are equal to the base input frequency divided by 768

when SLO/FST is low.

The CLK output is a 33% duty cycle clock signal designed to

drive the 80C86 and 80C88 microprocessors directly. CLK50

has a 50% duty cycle output synchronous with CLK, designed

to drive co-processors and peripherals requiring a 50% duty

cycle clock. When SLO/FST is high, CLK and CLK50 have out-

put frequencies which are 1/3 that of EFI/ OSC. When

SLO/FST is low, CLK and CLK50 have output frequencies

which are OSC (EFI) divided by 768.

PCLK is a peripheral clock signal with an output frequency

equal to the oscillator or EFI frequency divided by 6. PCLK has

a 50% duty cycle. PCLK is unaffected by SLO/FST. When the

82C85 is placed in the STOP mode, PCLK will remain in it’s

current state (logic high or logic low) until a RESET or START

command restarts the 82C85 clock circuitry. PCLK is negative-

edge synchronized with CLK and CLK50.

Clock Synchronization

The clock synchronization (CSYNC) input allows the output

clocks to be synchronized with an external event (such as

another 82C85 or 82C84A clock signal). CSYNC going active

causes all clocks (CLK, CLK50 and PCLK) to stop in the HIGH

state.

It is necessary to synchronize the CSYNC input to the EFI

clock external to the 82C85. This is accomplished with two flip-

flops when synchronizing two 82C85s and with three flip-flops

when synchronizing an 82C85 to an 82C84A (See Figure 6).

Multiple external flip-flops are necessary to minimize the occur-

rence of metastable (or indeterminate) states.

Ready Synchronization

Two READY inputs (RDY1, RDY2) are provided to accommo-

date two system busses. Each READY input is qualified by

(AEN1 and AEN2, respectively). The AEN signals validate their

respective RDY signals.

Synchronization is required for all asynchronous active-going

edges of either RDY input to guarantee that the RDY set up

and hold times are met. Inactive-going edges of RDY in nor-

mally ready systems do not require synchronization but must

satisfy RDY setup and hold as a matter of proper system

design.

The ASYNC input defines two modes of READY synchroniza-

tion operation. When ASYNC is LOW, two stages of synchroni-

zation are provided for active READY input signals. Positive-

going asynchronous READY inputs will first be synchronized to

flip-flop one at the rising edge of CLK (requiring a setup time

TR1VCH) and then synchronized to flip-flop two at the next fall-

ing edge of CLK, after which time the READY output will go

HIGH.

Negative-going asynchronous READY inputs will be synchro-

nized directly to flip-flop two at the falling edge of CLK, after

which time the READY output will go inactive. This mode of

operation is intended for use by asynchronous (normally not

ready) devices in the system which cannot be guaranteed by

design to meet the required RDY setup timing (TR1VCL) on

each bus cycle.

When ASYNC is high or left open, the first READY flip-flop is

bypassed in the READY synchronization logic. READY inputs

are synchronized by flip-flop two on the falling edge of CLK

before they are presented to the processor. This mode is avail-

able for synchronous devices that can be guaranteed to meet

the required RDY setup time. ASYNC can be changed on

every bus cycle to select the appropriate mode of synchroniza-

tion for each device in the system.

EFI

82C85

CSYNC

CSYNC

82C84A

CSYNC WITH 82C85(s)

CLOCK

SYNC

EFI

DQ

>



>



>



D

Q

Q

D

(TO OTHER

82C85s)

FIGURE 6. 82C85 AND 82C84A CSYNC SYNCHRONIZATION

METHODS