82C85

FN2976 Rev.0.00

Page 6 of 21

March 1997

FAST mode operation is enabled by each of two conditions:

•The SLO/FST input is HIGH and a START or reset command

is issued

• The SLO/FST input is held HIGH for at least 6 oscillator or

EFI cycles.

Alternate Operating Modes

Using alternate modes of operation (slow, stop-clock, stop-

oscillator) will reduce the average system operating power dis-

sipation in a static CMOS system (See Table 2). This does not

mean that system speed or throughput must be reduced.

When used appropriately, the slow, stopclock, stop-oscillator

modes can make your design more power efficient while main-

taining maximum system performance.

Stop-Oscillator Mode

When the 82C85 is stopped while in the crystal mode (F/C

LOW), the oscillator, in addition to all system clock signals (CLK,

CLK50 and PCLK), are stopped. CLK and CLK50 stop in the

high state. PCLK stops in it’s current state (high or low).

With the oscillator stopped, 82C85 power drops to it’s lowest

level. All clocks and oscillators are stopped. All devices in the

system which are driven by the 82C85 go into the lowest

power standby mode. The 82C85 also goes into standby and

requires a power supply current of less than 100

A.

Stop-Clock Mode

When the 82C85 is in the EFI mode (F/C HIGH) and a STOP

command is issued, all system clock signals (CLK, CLK50, and

PCLK) are stopped. CLK and CLK50 stop in the high state

when F/C is low and may stop in either the high or low state

when F/C is high. PCLK stops in its current state (high or low).

The 82C85 can also provide it’s own EFI source simply by con-

necting the OSC output to the EFI input and pulling the F/C

input HIGH. This puts the 82C85 into the External Frequency

Mode using it’s own oscillator as an external source signal

(See Figure 2). In this configuration, when the 82C85 is

stopped in the EFI mode, the oscillator continues to run. Only

the clocks to the CPU and peripherals (CLK, CLK50 and

PCLK) are stopped.

Oscillator/Clock Stop Operation

Three control lines determine when the 82C85 clock outputs or

oscillator will stop. These are S0, S1 and S2/STOP. These

three lines are designed to connect directly to the MAXimum

mode 80C86 and 80C88 status lines or to be driven by external

I/O signals (such as an 82C55A output port).

In the MAXimum mode configuration, the 82C85 will automati-

cally recognize a software HALT command from the 80C86 or

80C88 and stop the system clocks or oscillator. This allows

complete software control of the STOP function.

If the 80C86 or 80C88 is used in the MINimum mode, the

82C85 can be controlled using the S2/STOP input (with S0 and

S1 held high). This can be done using an external I/O control

line, such as from an 82C55A or by decoding the state of the

80C86 MINimum mode status signals.

82C85 status inputs S2/STOP, S1, S0 are sampled on the ris-

ing edge of CLK. The oscillator (F/C LOW only) and clock out-

puts are stopped by S2/STOP, S1, S0 being in the LHH state

on a low-to-high transition of CLK. This LHH state must follow

a passive HHH state occurring on the previous low-to-high

CLK transition. CLK and CLK50 will stop in the logic HIGH

state after two additional complete cycles of CLK. PCLK stops

in it’s current state (HIGH or LOW). This is true for both SLOW

and FAST mode operation.

80C86/88 Maximum Mode Clock Control

The 82C85 STOP function has been optimized for 80C86/88

MAXimum mode operation. In this mode, the three 82C85 status

inputs (S2/STOP, S1, S0) are connected directly to the MAXi-

mum mode status lines (S2, S1, S0) of the Intersil 80C86 or

80C88 static CMOS microprocessors (See Figure 3).

When in the MAXimum mode, the 80C86/88 status lines iden-

tify which type of bus cycle the CPU is starting to execute.

82C85 S2/STOP, S1 and S0 control input logic will recognize a

valid MAXimum mode software HALT executed by the 80C86

or 80C88. Once this state has been recognized, the 82C85

stops the clock (F/C HIGH) and oscillator (F/C LOW) operation.

FIGURE 2. STOP-CLOCK MODE USING 82C85 IN EFI MODE

WITH OSCILLATOR AS FREQUENCY SOURCE

X1

X2

EFI

F/C

S2/STOP

S1

S0

START

OSC

VCC

STOP

CONTROL

START

CONTROL

MN/MX

S0

S1

S2

S0

S1

S2/STOP

82C85

80C86/88

FIGURE 3. 82C85 STOP CONTROL USING 80C86/88

MAXIMUM MODE STATUS LINES