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©2016 Integrated Device Technology, Inc

Revision B November 16, 2016

General Description

The 831724 is a high-performance, differential HCSL clock/data

multiplexer and fanout buffer. The device is designed for the

multiplexing and fanout of high-frequency clock and data signals.

The device has two differential, selectable clock/data inputs. The

selected input signal is distributed to four low-skew differential HCSL

outputs. Each input pair accepts HCSL, LVDS and LVPECL levels.

The 831724 is characterized to operate from a 3.3V power supply.

Guaranteed input, output-to-output and part-to-part skew

characteristics make the 831724 ideal for those clock and data

distribution applications demanding well-defined performance and

repeatability. The 831724 supports the clock multiplexing and

distribution of PCI Express Generation 1, 2, and 3 clock signals.

Features

• 2:1 differential clock/data multiplexer with fanout

• Two selectable, differential inputs

• Each differential input pair can accept the following levels: HCSL,

LVDS, LVPECL.

• Four differential HCSL outputs

• Maximum input/output clock frequency: 350MHz

• Maximum input/output data rate: 700Mb/s (NRZ)

• LVCMOS interface levels for all control inputs

• PCI Express Gen 1,2,3 jitter compliant

• Input skew: 165ps (maximum)

• Output skew: 175ps (maximum)

• Part-to-part skew: 450ps (maximum)

• Full 3.3V supply voltage

• Available in lead-free (RoHS 6) package

• -40°C to 85°C ambient operating temperature

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32 31 30

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27 26 25

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2

3

4

5

6

7

8

24

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22

21

20

19

18

17

VDD

nOED

CLK0

nCLK0

CLK1

nCLK1

nOEA

VDD

nc

nOEC

nc

nc

nc

nc

SEL

nc

Block Diagram

QA

nQA

QB

nQB

QC

nQC

QD

nQD

IREF

CLK0

nCLK0

CLK1

nCLK1

SEL

Pulldown

Pullup

Pullup

Pullup

Pullup

Pullup/down

Pulldown

Pullup/down

Pulldown

0

1

Pin Assignment

831724I

32-Lead VFQFN

5mm x 5mm x 0.925mm package body

K Package

Top View

831724

Datasheet

Differential Clock/Data Multiplexer