7

Layout guidelines and design recommendations

A proper printed circuit board layout is essential for correct operation of any switch-mode converter and this is

also true for the VIPerGaN50. The main reasons for having a proper PCB layout are to:

• Provide clean signals to the IC, ensuring good immunity against external noises and switching noises

• Reduce the electromagnetic interferences, both radiated and conducted, to pass more easily the EMC

When designing an SMPS using VIPerGaN, the following basic rules should be considered:

•

Separating signal from power tracks: generally, traces carrying signal currents should run far from those

carrying pulsed currents or with quickly swinging voltages. Signal ground traces should be routed separately

from the power ground traces then connected one to the other using a single “star point”, placed close to the

IC.

•

The compensation network should be connected to the FB pin, maintaining the trace to GND as short as

possible. In case of a two-layer PCB, it is a good practice to route signal traces on one PCB side and power

traces on the other side.

•

Filtering sensitive pins: some crucial points of the circuit need or may need filtering. A small high

frequency bypass capacitor to GND might be useful to get a clean bias voltage for the signal part of the

IC and protect the IC itself during EFT/ESD tests. A low ESL ceramic capacitor (a few hundreds pF up to

0.1 μF) should be connected across VDD and GND, placed as close as possible to the IC. With flyback

topologies, when the auxiliary winding is used, it is suggested to connect the VDD capacitor on the auxiliary

return and then to the main GND using a single track. A small 10 nF capacitance is also required between

BR and GND to filter the noise in this high impedance path.

•

Keep power loops as confined as possible: minimize the area circumscribed by current loops where high

pulsed currents flow, in order to reduce its parasitic self-inductance and the radiated electromagnetic field:

this greatly reduces the electromagnetic interferences produced by the power supply during the switching. In

a flyback converter the most critical loops are the one including the input bulk capacitor, the power switch,

the power transformer, the one including the snubber, the one including the secondary winding, the output

rectifier, and the output capacitor.

•

Reduce line lengths: any wire acts as an antenna. With the very short rise times exhibited by EFT pulses,

any antenna has the capability of receiving high voltage spikes. By reducing line lengths, the level of

radiated energy that is received is reduced, and the resulting spikes from electrostatic discharges are lower.

This also keeps both resistive and inductive effects to a minimum. In particular, all of the traces carrying high

currents, especially if pulsed (tracks of the power loops) should be as short and fat as possible. It is a good

practice to minimize also the areas circumscribed by the paths from TB to GND and from BR to GND, to

ensure good immunity against EFT tests.

•

Optimize track routing: as levels of pickup from static discharges are likely to be greater closer to the

extremities of the board, it is wise to keep any sensitive lines away from these areas. Input and output lines

often need to reach the PCB edge at some stage, but they can be routed away from the edge as soon

as possible where applicable. Since vias are to be considered inductive elements, it is recommended to

minimize their number in the signal path and avoid them when designing the power path.

•

Improve thermal dissipation: an adequate copper area has to be provided under the EP pad as heatsink.

Since this pad is mechanically connected to the GaN substrate, which is also connected to GND, a large

copper area can be used without affecting the EMC performances.

VIPERGAN50

Layout guidelines and design recommendations

DS13888 - Rev 2

page 28/37