9P960

DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

IDT® DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

6

9P960

REV A 051811

Switching Characteristics1

TA = 0 - 70°C; Supply Voltage AVDD = 1.8V+/- 0.1V, VDD = 1.5 V +/- 5% (unless otherwise stated)

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Output enable time

ten

OE to any output

8

ns

Output disable time

t

dis

OE to any output

8

ns

Period jitter

tjit (per)

-30

30

ps

Half-period jitter

t

jit( hper )

-40

40

ps

Input Clock

1

2.5

4

v/ns

Output Enable (OE), (OS)

0.5

v/ns

Output clock slew rate

SLr1( o)

22.3

5.5

v/ns

t

jit(cc+)

040

ps

t

jit(cc-)

0-40

ps

Dynamic Phase Offset

t( )dyn

-20

20

ps

Static Phase Offset

t

( spo )

-60

0

60

ps

Output to Output Skew

tske w

100

ps

SSC modulation frequency

f

SSC MOD

30.00

33

kHz

SSC clock input frequency

deviation

f

SSC%

0.00

-0.50

%

Notes:

1. Switching characteristics guaranteed for application frequency range.

Cycle-to-cycle jitter

PLL will track SSC and

meet dynamic phase offset

in the specified range.

Input slew rate

SLr1 (i)