9P960

DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

IDT® DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

7

9P960

REV A 051811

General SMBus Serial Interface Information

How to Write

• Controller (host) sends a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through Byte

N+X-1

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

How to Read

• Controller (host) will send a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) will send a separate start bit

• Controller (host) sends the read address

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N+X-1

• IDT clock sends Byte 0 through Byte X (if X(H) was

written to Byte 8)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Write Operation

Controller (Host)

IDT (Slave/Receiver)

TstarT bit

Slave Address

WR

WRite

ACK

Beginning Byte = N

ACK

Data Byte Count = X

ACK

Beginning Byte N

ACK

O

O

O

O

O

O

Byte N + X - 1

ACK

PstoP bit

Read Address

Write Address

D5(H)

D4(H)

Index Block Read Operation

Controller (Host)

IDT (Slave/Receiver)

TstarT bit

Slave Address

WR

WRite

ACK

Beginning Byte = N

ACK

RT

Repeat starT

Slave Address

RD

ReaD

ACK

Data Byte Count=X

ACK

Beginning Byte N

ACK

O

O

O

O

O

O

Byte N + X - 1

N

Not acknowledge

PstoP bit