9P960

DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

IDT® DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

2

9P960

REV A 051811

Pin Descriptions

Pin#

Pin Name

Type

Pin Description

1

DDRAT0

OUT

"True" Clock of differential pair output.

2

DDRAC0

OUT

"Complementary" Clock of differential pair output.

3DDRAT1

OUT

"True" Clock of differential pair output.

4DDRAC1

OUT

"Complementary" Clock of differential pair output.

5

DDRAT2

OUT

"True" Clock of differential pair output.

6DDRAC2

OUT

"Complementary" Clock of differential pair output.

7

GND

PWR

Ground pin.

8

VDD1.8/1.5

PWR

Power supply, nominal 1.8 V or 1.5V

9

AGND

PWR

Analog Ground pin for Core PLL

10

AVDD1.8

PWR

1.8V Analog Power pin for Core PLL

11

SCLK

IN

Clock pin of SMBus circuitry, 5V tolerant.

12

SDATA

I/O

Data pin for S MBus circuitry, 5V tolerant.

13

VDD1.8/1.5

PWR

Power supply, nominal 1.8 V or 1.5V

14

DDRBT0

OUT

"True" Clock of differential pair output.

15

DDRBC0

OUT

"Complementary" Clock of differential pair output.

16

DDRBT1

OUT

"True" Clock of differential pair output.

17

DDRBC1

OUT

"Complementary" Clock of differential pair output.

18

DDRBT2

OUT

"True" Clock of differential pair output.

19

DDRBC2

OUT

"Complementary" Clock of differential pair output.

20

CLK_INTB_T

IN

True' reference clock input for ban k B.

21

CLK_INTB_C

IN

Complementary' reference clock i nput for bank B.

22

GND

PWR

Ground pin.

23

FB_INTB

IN

True single-ended feedback input, provides feedback signal to internal PLL for

synchronization with CLK INTB to el iminate phase error on bank B.

24

FB_OUTB

OUT

Feedback output, dedicated external feedback for bank B outputs.

25

DDRBC3

OUT

"Complementary" Clock of differential pair output.

26

DDRBT3

OUT

"True" Clock of differential pair output.

27

DDRBC4

OUT

"Complementary" Clock of differential pair output.

28

DDRBT4

OUT

"True" Clock of differential pair output.

29

DDRBC5

OUT

"Complementary" Clock of differential pair output.

30

DDRBT5

OUT

"True" Clock of differential pair output.

31

VDD1.8/1.5

PWR

Power supply, nominal 1.8 V or 1.5V

32

GND

PWR

Ground pin.

33

AGND

PWR

Analog Ground pin for Core PLL

34

AVDD1.8

PWR

1.8V Analog Power pin for Core PLL

35

GND

PWR

Ground pin.

36

VDD1.8/1.5

PWR

Power supply, nominal 1.8 V or 1.5V

37

DDRAC5

OUT

"Complementary" Clock of differential pair output.

38

DDRAT5

OUT

"True" Clock of differential pair output.

39

DDRAC4

OUT

"Complementary" Clock of differential pair output.

40

DDRAT4

OUT

"True" Clock of differential pair output.

41

DDRAC3

OUT

"Complementary" Clock of differential pair output.

42

DDRAT3

OUT

"True" Clock of differential pair output.

43

GND

PWR

Ground pin.

44

CLK_INTA_C

IN

Complementary' reference clock i nput for bank A.

45

CLK_INTA_T

IN

True' reference clock input for ban k A.

46

VDD1.8/1.5

PWR

Power supply, nominal 1.8 V or 1.5V

47

FB_INTA

IN

True single-ended feedback input, provides feedback signal to internal PLL for

synchronization with CLK INTA to el imate phase erro r on bank A.

48

FB_OUTA

OUT

Feedback output, dedicated external feedback for bank A outputs.