ILPS28QSW datasheet(24/52 Pages) STMICROELECTRONICS

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Digital interfaces

8.1

Serial interfaces

The registers embedded in the ILPS28QSW may be accessed through the I²C, MIPI I3CSM serial interfaces.

Table 12. Serial interface pin description

Pin name

Pin description

SCL

I²C / MIPI I3CSM serial clock (SCL)

SDA

I²C / MIPI I3CSM serial data (SDA)

8.2

I²C serial interface

The ILPS28QSW I²C is a bus slave. The I²C is employed to write data into registers whose content can also be

read back.

The relevant I²C terminology is given in the following table.

Table 13. I²C terminology

Term

Description

Transmitter

The device that sends data to the bus

Receiver

The device that receives data from the bus

Master

The device that initiates a transfer, generates clock signals, and terminates a transfer

Slave

The device addressed by the master

There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The

latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines have to be

connected to VDD through pull-up resistors.

The I²C interface is compliant with fast mode plus (1 MHz) I²C standards as well as with the normal mode.

8.2.1

I²C operation

The transaction on the bus is started through a start (ST) signal. A start condition is defined as a high to low

transition on the data line while the SCL line is held high. After the master has transmitted this, the bus is

considered busy. The next data byte transmitted after the start condition contains the address of the slave in the

first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the

slave. When an address is sent, each device in the system compares the first seven bits after a start condition

with its address. If they match, the device considers itself addressed by the master.

The 7-bit slave address (SAD) associated to the ILPS28QSW is 1011100b = 5Ch.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge

pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the

acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each

byte of data received.

The I²C embedded inside the ASIC behaves like a slave device and the following protocol must be adhered

to. After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK),

an 8-bit subaddress is transmitted (SUB). The IF_ADD_INC bit in CTRL_REG2 (11h) enables subaddress auto

increment (IF_ADD_INC is 1 by default), so if IF_ADD_INC = 1 the SUB (subaddress) is automatically increased

to allow multiple data read/write.

The slave address is completed with a read/write bit. If the bit is 1 (read), a repeated start (SR) condition

must be issued after the two subaddress bytes; if the bit is 0 (write) the master transmits to the slave with

direction unchanged. Table 14 explains how the SAD+read/write bit pattern is composed, listing all the possible

configurations.

ILPS28QSW

Digital interfaces

DS13905 - Rev 1

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