ILPS28QSW datasheet(25/52 Pages) STMICROELECTRONICS

25 / 52 page

Table 14. SAD+read/write patterns

Command

SAD[6:0]

R/W

SAD + R/W

Read

1011100

10111001 (B9h)

Write

1011100

10111000 (B8h)

Table 15. Transfer when master is writing one byte to slave

Master

SAD+ W

SUB

DATA

Slave

SAK

Table 16. Transfer when master is writing multiple bytes to slave

Master

SAD+ W

SUB

DATA

Slave

SAK

Table 17. Transfer when master is receiving (reading) one byte of data from slave

Master

SAD+ W

SUB

SAD+ R

NMAK

Slave

SAK

DATA

Table 18. Transfer when master is receiving (reading) multiple bytes of data from slave

Master

SAD+

SUB

SAD+

MAK

NMAK

Slave

SAK

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred

per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a slave receiver does not

acknowledge the slave address (that is, it is not able to receive because it is performing some real-time function),

the data line must be kept high by the slave. The master can then abort the transfer. A low to high transition on

the SDA line while the SCL line is high is defined as a stop condition. Each data transfer must be terminated by

the generation of a stop (SP) condition.

In the presented communication format MAK is master acknowledge and NMAK is no master acknowledge.

ILPS28QSW

I²C serial interface

DS13905 - Rev 1

page 25/52

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