LIS2DUXS12 datasheet(21/104 Pages) STMICROELECTRONICS

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The FIFO buffer can work according to six different modes:

•

Bypass mode

•

FIFO mode

•

Continuous mode

•

Continuous-to-FIFO mode

•

Bypass-to-continuous

•

Bypass-to-FIFO

Each mode is selected by the FIFO_MODE[2:0] bits in the FIFO_CTRL (15h) register. A programmable FIFO

watermark is selected in the FIFO_WTM (16h) register.

FIFO status is available in the FIFO_STATUS1 (26h) and FIFO_STATUS2 (27h) registers and can be used to

generate dedicated interrupts on the INT1 and INT2 pins using the CTRL2 (11h) and CTRL3 (12h) registers.

The FIFO_WTM_IA bit in the FIFO_STATUS1 (26h) register goes to 1 when the number of unread samples

is greater than or equal to FTH[6:0] in FIFO_WTM (16h). If FTH[6:0] is equal to 0, the FIFO_WTM_IA bit in

FIFO_STATUS1 (26h) goes to 0.

The FIFO_OVR_IA bit in FIFO_STATUS1 (26h) is equal to 1 if a FIFO sample is overwritten.

FSS[7:0] in FIFO_STATUS2 (27h) contains stored data levels of unread samples.

When FSS[7:0] is equal to 00000000, FIFO is empty. When FSS[7:0] is equal to 10000000, FIFO is full and the

unread samples are 128.

5.1.1

Bypass mode

In bypass mode FIFO_CTRL (15h) (FIFO_MODE[2:0] = 000), the FIFO is not operational, no data is collected in

FIFO memory, and it remains empty with only the actual sample available in the output registers.

Bypass mode is also used to reset the FIFO when in FIFO mode.

5.1.2

FIFO mode

In FIFO mode FIFO_CTRL (15h) (FIFO_MODE[2:0] = 001) data from the output channels are stored in the FIFO

memory until it is full. When 128 unread samples are stored in memory, data collecting is stopped.

To reset FIFO content, bypass mode should be selected by writing FIFO_CTRL (15h) (FIFO_MODE[2:0]) to 000.

After this reset command, it is possible to restart FIFO mode, writing FIFO_CTRL (15h) (FIFO_MODE[2:0]) to

001.

5.1.3

Continuous mode

Continuous mode FIFO_CTRL (15h) (FIFO_MODE[2:0] = 110) provides a continuous FIFO update: when 128

unread samples are stored in memory, as new data arrives, the oldest data is discarded and overwritten by the

newer.

A FIFO threshold flag FIFO_WTM_IA bit in FIFO_STATUS1 (26h) is asserted when the number of unread

samples in FIFO is greater than or equal to FTH[6:0] in FIFO_WTM (16h).

It is possible to route the FIFO_WTM_IA bit to the INT1 pin by writing the INT1_FIFO_TH bit to 1 in register

CTRL2 (11h) or to the INT2 pin by writing the INT2_FIFO_TH bit to 1 in register CTRL3 (12h).

If an overrun occurs, the oldest sample in FIFO is overwritten and the FIFO_OVR_IA flag in FIFO_STATUS1

(26h) is asserted.

5.1.4

Continuous-to-FIFO mode

In continuous-to-FIFO mode FIFO_MODE[2:0] = 011 in the FIFO_CTRL (15h) register, FIFO operates in

continuous mode and FIFO mode starts upon an edge trigger event. When the FIFO is full, data collecting is

stopped. The trigger event could be single/double/triple-tap, wake-up, free-fall, 6D interrupt or any combination of

these events, but every interrupt has to be routed to the corresponding pin to be used as a trigger.

LIS2DUXS12

FIFO

DS14035 - Rev 2

page 21/104

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