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DFE252012F-R47M 数据表(PDF) 34 Page - Analog Devices |
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DFE252012F-R47M 数据表(HTML) 34 Page - Analog Devices |
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34 / 122 page ![]() Table 2. Device Configuration by RCFG1 (continued) RCFG1 (Ω) I2C SLAVE ADDRESS (7-BIT ADDRESS) MFIO1 MFIO2 MFIO3 MFIO4 MFIO5 MFIO6 MFIO7 MFIO8 48.7k 7'h61 (110 0001) FPSI POK_M1 FPWM_M1 CLKDET_M1 VB_GLB RSTINB TWARNB RSTOB 56.2k 7'h62 (110 0010) FPSI POK_M1 FPWM_M1 CLKDET_M1 VB_GLB RSTINB TWARNB RSTOB 64.9k 7'h63 (110 0011) FPSI POK_M1 FPWM_M1 CLKDET_M1 VB_GLB RSTINB TWARNB RSTOB 75.0k 7'h60 (110 0000) Factory Option 86.6k 7'h61 (110 0001) 100k 7'h62 (110 0010) ≥ 115k 7'h63 (110 0011) Table 3 decodes the default selection options for the peak current limit of master phases and the switching frequency setting. Once latched, the Mx_ILIM[1:0] and the Mx_FREQ[1:0] bits reflect the selected options. The decoded values for RCFG2 ≥ 115kΩ are programmable at the factory. Table 3. Device Configuration by RCFG2 RCFG2 (Ω) M1_ILIM (A) M2_ILIM (A) M3_ILIM (A) M4_ILIM (A) Mx_FREQ (MHz) ≤ 95.3 5.5 5.5 5.5 5.5 1.0 200 5.5 5.5 5.5 5.5 1.5 309 5.5 5.5 5.5 3.5 1.0 422 5.5 5.5 5.5 3.5 1.5 536 5.5 5.5 3.5 5.5 1.0 649 5.5 5.5 3.5 5.5 1.5 768 5.5 5.5 3.5 3.5 1.0 909 5.5 5.5 3.5 3.5 1.5 1.05k 5.5 3.5 5.5 5.5 1.0 1.21k 5.5 3.5 5.5 5.5 1.5 1.40k 5.5 3.5 5.5 3.5 1.0 1.62k 5.5 3.5 5.5 3.5 1.5 1.87k 5.5 3.5 3.5 5.5 1.0 2.15k 5.5 3.5 3.5 5.5 1.5 2.49k 5.5 3.5 3.5 3.5 1.0 2.87k 5.5 3.5 3.5 3.5 1.5 3.74k 3.5 5.5 5.5 5.5 1.0 8.06k 3.5 5.5 5.5 5.5 1.5 12.4k 3.5 5.5 5.5 3.5 1.0 16.9k 3.5 5.5 5.5 3.5 1.5 21.5k 3.5 5.5 3.5 5.5 1.0 26.1k 3.5 5.5 3.5 5.5 1.5 MAX77542 16VIN/16A, Quad-Phase High-Efficiency Buck Converter www.analog.com Analog Devices | 34 |
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