ICS831721AGI REVISION A FEBRUARY 3, 2014

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©2014 Integrated Device Technology, Inc.

ICS831721I Data Sheet

DIFFERENTIAL CLOCK/DATA MULTIPLEXER

Table 5. PCI Express Jitter Specifications, VDD = 3.3V ± 0.3V, TA= -40°C to 85°C

NOTE: The source generator used in the PCI Express Jitter measurements is Stanford Research Systems CG635 2.0GHz Synthesized Clock

Generator.

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.

NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1

is 86ps peak-to-peak for a sample size of 106 clock periods.

NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS

(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).

NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express

Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.

NOTE 4: This parameter is guaranteed by characterization. Not tested in production.

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

PCIe Industry

Specification

Units

tJ

(PCIe Gen 1)

Phase Jitter

Peak-to-Peak

NOTE 1, 4

ƒ = 100MHz,

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

6.77

11.2

86

ps

tREFCLK_HF_RMS

(PCIe Gen 2)

Phase Jitter RMS;

NOTE 2, 4

ƒ = 100MHz,

High Band:1.5Hz - Nyquist

(clock frequency/2)

0.59

1.01

3.1

ps

tREFCLK_LF_RMS

(PCIe Gen 2)

Phase Jitter RMS;

NOTE 2, 4

ƒ = 100MHz,

Low Band: 10kHz - 1.5Hz

0.03

0.07

3.0

ps

tREFCLK_RMS

(PCIe Gen 3)

Phase Jitter RMS;

NOTE 3, 4

ƒ = 100MHz,

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

0.112

0.185

0.8

ps