ICS831721AGI REVISION A FEBRUARY 3, 2014

2

©2014 Integrated Device Technology, Inc.

ICS831721I Data Sheet

DIFFERENTIAL CLOCK/DATA MULTIPLEXER

Pin Descriptions and Characteristics

Table 1. Pin Descriptions

NOTE: Pullup and pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Function Tables

Table 3A. nOE Configuration Table

NOTE: nOE is an asynchronous control.

Table 3B. SEL Configuration Table

NOTE: SEL is an asynchronous control.

Number

Name

Type

Description

1

CLK0

Input

Pulldown

Non-inverting clock/data input 0.

2

nCLK0

Input

Pullup/Pulldown Inverting differential clock input 0. VDD/2 default when left floating.

3, 8, 11, 14

VDD

Power

Positive power supply.

4

CLK1

Input

Pulldown

Non-inverting clock/data input 1.

5

nCLK1

Input

Pullup/Pulldown Inverting differential clock input 1. VDD/2 default when left floating.

6, 10

GND

Power

Power supply ground.

7

nc

Unused

No connect.

9

nOE

Input

Pullup

Output enable. See Table 3A for function. LVCMOS/LVTTL interface levels.

12, 13

Q, nQ

Output

Differential output pair. HCSL interface levels.

15

SEL

Input

Pulldown

Input select. See Table 3B for function. LVCMOS/LVTTL interface levels.

16

IREF

Input

An external fixed precision resistor (475

) from this pin to ground provides a

reference current used for the differential current-mode Q, nQ outputs.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

CIN

Input Capacitance

4

pF

RPULLDOWN

Input Pulldown Resistor

51

k



RPULLUP

Input Pullup Resistor

51

k



Input

Operation

nOE

0

Output Q, nQ is enabled.

1 (default)

Output Q, nQ is in a high-impedance state.

Input

Selected Input

SEL

0 (default)

CLK0, nCLK0

1

CLK1, nCLK1