ICS831721AGI REVISION A FEBRUARY 3, 2014

5

©2014 Integrated Device Technology, Inc.

ICS831721I Data Sheet

DIFFERENTIAL CLOCK/DATA MULTIPLEXER

AC Electrical Characteristics

Table 6. HCSL AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Measured from the differential input cross point to the differential output crossing point.

NOTE 2: Defined as skew between input paths on the same device, using the same input signal levels, measured at one specific output at the

differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using

the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 5: Measurement taken from differential waveform.

NOTE 6: Measurement from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic

through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

NOTE 7: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is

allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section.

NOTE 8: Measurement taken from single-ended waveform.

NOTE 9: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.

NOTE 10: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.

NOTE 11: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.

See Parameter Measurement Information Section

NOTE 12: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement. See Parameter Measurement Information Section.

NOTE 13: Defined as the total variation of all crossing voltage of rising Q and falling nQ. This is the maximum allowed variance in the VCROSS

for any particular system. See Parameter Measurement Information Section.

NOTE 14: Input duty cycle must be 50%.

NOTE 15: Q, nQ output measured differentially. See MUX Isolation Diagram in Parameter Measurement Information Section.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fOUT

Output Frequency

700

MHz

tjit

Buffer Additive Phase Jitter,

RMS; refer to Additive Phase

Jitter Plot

100MHz, Integration Range:

12kHz – 20MHz

0.314

0.337

ps

tPD

Propagation Delay, NOTE 1

Any CLKx, nCLKx to Q, nQ

2

2.4

ns

tsk(i)

Input Skew; NOTE 2

55

ps

tsk(pp)

Part-to-Part Skew;

NOTE 3, 4

400

ps

Edge Rate

Rise/Fall Edge Rate;

NOTE 5, 6

0.6

4.0

V/ns

VRB

Ringback Voltage;

NOTE 5, 7

-100

100

V

VMAX

Absolute Max Output

Voltage; NOTE 8, 9

1150

mV

VMIN

Absolute Min Output Voltage;

NOTE 8, 10

-300

mV

VCROSS

Absolute Crossing Voltage;

NOTE 8, 11, 12

250

550

mV

V

CROSS

Total Variation of VCROSS

over all edges;

NOTE 8, 11, 13

140

mV

odc

Output Duty Cycle;

NOTE 14

fOUT < 312.5MHz

46

54

%

fOUT > 312.5MHz

43

57

%

MUXISOL

Mux Isolation;

NOTE 15

ƒ = 100MHz

80

dB