DATASHEET

Differential Clock/Data Multiplexer

ICS831721I

ICS831721AGI REVISION A FEBRUARY 3, 2014

1

©2014 Integrated Device Technology, Inc.

General Description

The ICS831721I is a high-performance, differential HCSL clock/data

multiplexer and fanout buffer. The device is designed for the

multiplexing of high-frequency clock and data signals. The device has

two differential, selectable clock/data inputs. The selected input

signal is output at one differential HCSL output. Each input pair

accepts HCSL, LVDS, and LVPECL levels. The ICS831721I is

characterized to operate from a 3.3V power supply. Guaranteed

input, output-to-output and part-to-part skew characteristics make

the ICS831721I ideal for those clock and data distribution

applications demanding well-defined performance and repeatability.

The ICS831721I supports the clock multiplexing and distribution of

PCI Express Generation 1, 2 and 3 clock signals.

Features

• 2:1 differential clock/data multiplexer with fanout

• Two selectable, differential inputs

• Each differential input pair can accept the following levels: HCSL,

LVHSTL, LVDS and LVPECL

• One differential HCSL output

• Maximum input/output clock frequency: 700MHz (maximum)

• Maximum input/output data rate: 1400Mb/s (NRZ)LVCMOS

interface levels for all control inputs

• Input skew: 55ps (maximum)

• Part-to-part skew: 400ps (maximum)

• Full 3.3V supply voltage

• Available in lead-free (RoHS 6) 16 TSSOP package

• -40°C to 85°C ambient operating temperature

Block Diagram

Pin Assignment

ICS831721I

16-Lead TSSOP

4.4mm x 5.0mm x 0.925mm package body

G Package

Top View

IREF

CLK0

nCLK0

CLK1

nCLK1

SEL

nOE

Q

nQ

0

1

Pulldown

Pullup/down

Pulldown

Pullup/down

Pulldown

Pullup/down

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VDD

nc

GND

nCLK1

CLK1

VDD

nCLK0

CLK0

IREF

SEL

VDD

nQ

Q

VDD

GND

nOE