ADN2530

Rev. A | Page 10 of 20

THEORY OF OPERATION

As shown in Figure 1, the ADN2530 consists of an input

stage and two voltage-controlled current sources for bias and

modulation. The bias current is available at the IBIAS pin. It is

controlled by the voltage at the BSET pin and can be monitored

at the IBMON pin. The differential modulation current is

available at the IMODP and IMODN pins. It is controlled by

the voltage at the MSET pin. The output stage implements the

active back-termination circuitry for proper transmission line

matching and power consumption reduction. The ADN2530

can drive a load with differential resistance ranging from 35 Ω

to 140 Ω. The excellent back-termination in the ADN2530

absorbs signal reflections from the TOSA end of the output

transmission lines, enabling excellent optical eye quality to be

achieved even when the TOSA end of the output transmission

lines is significantly misterminated.

INPUT STAGE

The input stage of the ADN2530 converts the data signal applied

to the DATAP and DATAN pins to a level that ensures proper

operation of the high speed switch. The equivalent circuit of the

input stage is shown in Figure 22.

VCC

50

Ω

50

Ω

VCC

DATAP

DATAN

VCC

Figure 22. Equivalent Circuit of the Input Stage

The DATAP and DATAN pins are terminated internally with a

100 Ω differential termination resistor. This minimizes signal

reflections at the input that could otherwise lead to degradation

in the output eye diagram. It is not recommended to drive the

ADN2530 with single-ended data signal sources.

The ADN2530 input stage must be ac-coupled to the signal

source to eliminate the need for matching between the common-

mode voltages of the data signal source and the input stage of

the driver (see Figure 23). The ac-coupling capacitors should

have an impedance less than 50 Ω over the required frequency

range. Generally, this is achieved using 10 nF to 100 nF

capacitors.

ADN2530

DATAP

DATAN

C

C

50

Ω

50

Ω

DATA SIGNAL SOURCE

Figure 23. AC Coupling the Data Source to the ADN2530 Data Inputs

BIAS CURRENT

The bias current is generated internally using a voltage-to-current

converter consisting of an internal operational amplifier and a

transistor, as shown in Figure 24.

GND

200Ω

800Ω

10Ω

VCC

IBMON

BSET

IBMON

ADN2530

IBIAS

200Ω

IBIAS

Figure 24. Voltage-to-Current Converter Used to Generate IBIAS

The BSET to IBIAS voltage-to-current conversion factor is

set at 20 mA/V by the internal resistors, and the bias current is

monitored at the IBMON pin using a current mirror with a gain

equal to 1/20. By connecting a 750 Ω resistor between IBMON

and GND, the bias current can be monitored as a voltage across

the resistor. A low temperature coefficient precision resistor

temperature contributes to the overall error budget for the IBIAS

monitor voltage. If the IBMON voltage is being connected to an

ADC to minimize errors due to voltage drops on the ground

plane. See the Design Example section for example calculations

of the accuracy of the IBIAS monitor as a percentage of the

nominal IBIAS value.