ADN2530

Rev. A | Page 16 of 20

DESIGN EXAMPLE

This design example covers:

• Headroom calculations for IBIAS, IMODP, and IMODN pins.

• Calculation of the typical voltage required at the BSET

and MSET pins to produce the desired bias and

modulation currents.

• Calculations of the IBIAS monitor accuracy over the IBIAS

current range.

This design example assumes that the impedance of the

TOSA is 60 Ω, the forward voltage of the VCSEL at low current

Headroom Calculations

To ensure proper device operation, the voltages on the IBIAS,

IMODP, and IMODN pins must meet the compliance voltage

specifications in Table 1.

Considering the typical application circuit shown in Figure 39,

the voltage at the IBIAS pin can be written as

where:

VCC is the supply voltage.

For proper operation, the minimum voltage at the IBIAS pin

should be greater than 0.55 V, as specified by the minimum

IBIAS compliance specification in Table 1.

Assuming that the voltage drop across the 50 Ω transmission lines

The maximum voltage at the IBIAS pin must be less than the

maximum IBIAS compliance specification as described by

For this example,

To calculate the headroom at the modulation current pins

(IMODP and IMODN), the voltage has a dc component equal

to VCC due to the ac-coupled configuration and a swing equal

ADN2530, the voltage at each modulation output pin should be

within the normal operation region shown in Figure 35.

Assuming the dc voltage drop across L1, L2, L3, and L4 = 0 V

and IMOD = 10 mA, the minimum voltage at the modulation

output pins is equal to

VCC − (IMOD × 50)/2 = VCC − 0.25

VCC − 0.25 > VCC − 0.7 V, which satisfies the requirement

The maximum voltage at the modulation output pins is equal to

VCC + (IMOD × 50)/2 = VCC + 0.25

VCC + 0.25 < VCC + 0.7 V, which satisfies the requirement

Headroom calculations must be repeated for the minimum and

maximum values of the required IBIAS and IMOD ranges to

ensure proper device operation over all operating conditions.

BSET and MSET Pin Voltage Calculation

To set the desired bias and modulation currents, the BSET and

MSET pins of the ADN2530 must be driven with the appropriate

dc voltage. The voltage range required at the BSET pin to generate

the required IBIAS range can be calculated using the BSET voltage

to IBIAS gain specified in Table 1. Assuming that IBIAS = 10 mA

is given by

V

5

.

0

20

10

mA/V

20

(mA)

=

=

=

IBIAS

V

BSET

The BSET voltage range can be calculated using the required

IBIAS range and the minimum and maximum BSET voltage to

IBIAS gain values specified in Table 1.

The voltage required at the MSET pin to produce the desired

modulation current can be calculated using

K

IMOD

V

where

K is the MSET voltage to IMOD ratio.

The value of K depends on the actual resistance of the TOSA

and can be obtained from Figure 34. For a TOSA resistance of

60 Ω, the typical value of K = 24 mA/V. Assuming that IMOD =

10 mA and using the preceding equation, the MSET voltage is

given by

V

42

.

0

24

10

mA/V

24

(mA)

=

=

=

IMOD

V

MSET

The MSET voltage range can be calculated using the required

IMOD range and the minimum and maximum K values. These can

be obtained from the minimum and maximum curves in Figure 34.