ISL8200MM

FN7690 Rev 2.00

Page 14 of 24

Mar 15, 2013

The output voltage accuracy can be improved by maintaining the

impedance at VOUTSET (internal VSEN1+) at or below 1kΩ

effective impedance. Note: the impedance between VSEN1+ and

VSEN1- is about 600kΩ.

Input Supply Voltage Considerations

The module has minimum input voltage at a given output

voltage, which needs to be a minimum of 1.43x output voltage if

operating at FSW = 700kHz switching frequency. This is due to

the Minimum PWM OFF Time (tMIN-OFF).

The equation to determine the minimum VIN to support the

required VOUT is given by Equations 2 and 3: it is recommended

to add 0.5V to the result to account for temperature variations.

tSW = switching period = 1/FSW

for the 700kHz switching frequency = 1428ns

The voltage on PVCC is recommended to be 5V or above for

sufficient gate drive voltage. This can be accomplished by

directly connecting a voltage source greater than or equal to 5V

(but below 5.6V) to both VIN and PVCC when VIN is below 5V.

Selection of the Input Capacitor

The input filter capacitor should be based on how much ripple

the supply can tolerate on the DC input line. The larger the

capacitor, the less ripple expected, but consideration should be

taken for the higher surge current during power-up. The

ISL8200MMREP provides the soft-start function that controls

and limits the current surge. The value of the input capacitor can

be calculated by Equation 4:

Where:

CIN is the input capacitance (μF)

IIN is the input current (A)

t is the turn on time of the high-side switch (μs)

V is the allowable peak-to-peak voltage (V)

In addition to the bulk capacitance, some low Equivalent Series

Inductance (ESL) ceramic capacitance is recommended to

decouple between the drain terminal of the high-side MOSFET

and the source terminal of the low side MOSFET. This is used to

reduce the voltage ringing created by the switching current

across parasitic circuit elements.

Output Capacitors

The ISL8200MMREP is designed for low output voltage ripple.

The output voltage ripple and transient requirements can be met

with bulk output capacitors (COUT) with low enough Equivalent

Series Resistance (ESR). COUT can be a low ESR tantalum

capacitor, a low ESR polymer capacitor or a ceramic capacitor.

The typical capacitance is 330μF and decoupled ceramic output

capacitors are used per phase. The internally optimized loop

compensation provides sufficient stability margins for all

ceramic capacitor applications with a recommended total value

of 300μF per phase. Additional output filtering may be needed if

further reduction of output ripple or dynamic transient spike is

required.

Functional Description

Initialization

The ISL8200MMREP requires VCC and PVCC to be biased by a

single supply. Power-On Reset (POR) circuits continually monitor

the bias voltages (PVCC and VCC) and the voltage at EN pin. The

POR function initiates soft-start operation 384 clock cycles after

the EN pin voltage is pulled to be above 0.8V, all input supplies

exceed their POR thresholds and the PLL locking time expires.

The enable pin can be used as a voltage monitor and to set

desired hysteresis with an internal 30μA sinking current going

through an external resistor divider. The sinking current is

disengaged after the system is enabled. This feature is especially

designed for applications that require higher input rail POR for

better undervoltage protection. For example, in 12V applications,

RUP = 53.6k and RDOWN = 5.23k will set the turn-on threshold

(VEN_RTH) to 10.6V and turn-off threshold (VEN_FTH) to 9V, with

1.6V hysteresis (VEN_HYS).

During shutdown or fault conditions, the soft-start is quickly reset

while UGATE and LGATE immediately change state (<100ns)

upon the input dropping below POR.

Voltage Feed-forward

The voltage applied to the FF pin is fed to adjust the sawtooth

amplitude of the channel. The amplitude the sawtooth is set to

1.25x the corresponding FF voltage when the module is enabled.

This configuration helps to maintain a constant gain

(GM = VIN •DMAX/VRAMP) and input voltage to achieve

optimum loop response over a wide input voltage range. The

sawtooth ramp offset voltage is 1V (equal to 0.8V*1.25), and the

peak of the sawtooth is limited to VCC - 1.4V. With VCC = 5.4V, the

ramp has a maximum peak-to-peak amplitude of VCC - 2.4V

(equal to 3V); thus the feed-forward voltage effective range is

typically 3x as the ramp amplitude ranges from 1V to 3V.

A 384 cycle delay is added after the system reaches its rising

POR and prior to the soft-start. The RC timing at the FF pin should

be sufficiently small to ensure that the input bus reaches its

static state and the internal ramp circuitry stabilizes before soft-

start. A large RC could cause the internal ramp amplitude not to

synchronize with the input bus voltage during output start-up or

when recovering from faults. A 1nF capacitor is recommended as

a starting value for typical application. The voltage on the FF pin

needs to be above 0.7V prior to soft-start and during PWM

switching to ensure reliable regulation. In a typical application,

FF pin can be shorted to EN pin.

PVIN_MIN

VOUT tSW



tSW tMIN_OFF

–

------------------------------------------

=

(EQ. 2)

PVIN_MIN

1.43 VOUT



=

(EQ. 3)

CIN

IIN t



V

-------------------

=

(EQ. 4)

FIGURE 21. SOFT-START INITIALIZATION LOGIC

VCC POR

PVCC POR

EN POR

SOFT-START

HIGH = ABOVE POR; LOW = BELOW POR

OF MODULE

AND

384

PLL LOCKING

CYCLES