ISL8200MM

FN7690 Rev 2.00

Page 16 of 24

Mar 15, 2013

The ISL8200MMREP has the ability to work under a pre-charged

output. The PWM outputs will not feed to the drivers until the first

PWM pulse is seen. The low side MOSFET is being held low for

the first clock cycle to provide charge for the bootstrap capacitor.

If the pre-charged output voltage is greater than the final target

level but less than the 113% setpoint, switching will not start

until the output voltage is reduced to the target voltage and the

first PWM pulse is generated. The maximum allowable

pre-charged level is 113%. If the pre-charged level is above 113%

but below 120%, the output will hiccup between 113% (LGATE

turns on) and 87% (LGATE turns off) while EN is pulled low. If the

pre-charged load voltage is above 120% of the targeted output

voltage, then the controller will be latched off and not be able to

power-up.

The recommended sequence to start-up at cold temperature

is to hold EN pin to ground and release it after PVIN and VIN

voltage has reached steady state.

Power-Good

The Power-Good comparators monitor the voltage on the internal

VMON1 pin. The trip points are shown in Figure 26. PGOOD will

not be asserted until after the completion of the soft-start cycle.

The PGOOD pulls low upon both EN’s disabling it or the internal

VMON1 pin’s voltage is out of the threshold window. PGOOD will

not be asserted until after the completion of the soft-start cycle.

PGOOD will not pull low until the fault is present for three

consecutive clock cycles.

The UV indication is not enabled until the end of soft-start. In a UV

event, if the output drops below -13% of the target level due to

some reason (cases when EN is not pulled low) other than OV,

OC, OT, and PLL faults, PGOOD will be pulled low.

Current Share

The IAVG_CS is the current of the module. ISHARE and ISET pins

source a copy of IAVG_CS with 15μA offset, i.e., the full scale will

be 123μA.

The share bus voltage (VISHARE) set by an external resistor

(RISHARE = RISET/NCTRL) represents the average current of all

active modules. The voltage (VISET) set by RISET represents the

average current of the corresponding module and is compared

with the share bus (VISHARE). The current share error signal

(ICSH_ER) is then fed into the current correction block to adjust

each module’s PWM pulse accordingly. The current share

function provides at least 10% overall accuracy between ICs, up

to 3 phases when using 1% resistor to sense 10mV signal. The

current share bus works for up to 6-phase. Using current sharing

feature of ISL8200MMREP below -40°C ambient is not

recommended. However, the operation of a single module is

acceptable.

When there is only one module in the system, the ISET and

ISHARE pins can be shorted together and grounded via a single

resistor to ensure zero share error - a resistor value of 5k

(paralleling 10k on ISET and ISHARE) will allow operation up to

the OCP level.

Overvoltage Protection (OVP)

The Overvoltage (OV) protection indication circuitry monitors the

voltage on the internal VMON1 pin.

OV protection is active from the beginning of soft-start. An OV

condition (>120%) would latch the IC off (the high-side MOSFET

to latch off permanently; the low-side MOSFET turns on

immediately at the time of OV trip and then turns off

permanently after the output voltage drops below 87%). The EN

and PGOOD are also latched low at OV event. The latch condition

can be reset only by recycling VCC.

There is another non-latch OV protection (113% of target level).

At the condition of EN low and the output over 113% OV, the

lower side MOSFET will turn on until the output drops below 87%.

This is to protect the overall power trains in case of a single

channel of a multi-module system detecting OV. The low-side

MOSFET always turns on at the conditions of EN = LOW and the

output voltage above 113% (all EN pins are tied together) and

turns off after the output drops below 87%. Thus, in a high phase

count application (multi-module mode), all cascaded modules

can latch off simultaneously via the EN pins (EN pins are tied

together in multiphase mode), and each IC shares the same sink

current to reduce the stress and eliminate the bouncing among

phases.

Over-Temperature Protection (OTP)

When the junction temperature of the IC is greater than +150°C

(typically), EN pin will be pulled low to inform other cascaded

channels via their EN pins. All connected ENs stay low and

release after the IC’s junction temperature drops below +125°C

(typically), a +25°C hysteresis (typically).

Overcurrent Protection (OCP)

The OCP function is enabled at start-up. The module’s output

current (ICS1) plus a fixed internal 15μA offset forms a voltage

(VISHARE) across the external resistor, RISHARE. VISHARE is

compared with a precision internal 1.2V threshold. The Channel

Overcurrent Limit ‘108μA OCP’ comparator, waits 7-cycles before

monitoring for an OCP condition.

FIGURE 26. POWER-GOOD THRESHOLD WINDOW

-13%

-9%

VREF

+9%

+13%

VMON1

END OF SS1

AND

PGOOD

CHANNEL 1 UV/OV

+20%

PGOOD

PGOOD LATCH OFF AFTER 120% OV