ISL8200MM

FN7690 Rev 2.00

Page 18 of 24

Mar 15, 2013

By connecting the FSYNC_IN pin to an external square pulse

waveform (such as the CLKOUT signal, typically 50% duty cycle

from another ISL8200MMREP), the ISL8200MMREP will

synchronize its switching frequency to the fundamental

frequency of the input waveform. The maximum voltage to the

FSYNC_IN pin is VCC + 0.3V. The Frequency Synchronization

feature will synchronize the leading edge of the CLKOUT signal

with the falling edge of Channel 1’s PWM clock signal. CLKOUT is

not available until the PLL locks.

The locking time is typically 130μs for FSW = 500kHz. EN is not

released for a soft-start cycle until FSYNC is stabilized and the

PLL is in locking. It is recommended to connect all EN pins

together in multiphase configuration.

The loss of a synchronization signal for 13 clock cycles causes

the IC to be disabled until the PLL returns locking, at which point

a soft-start cycle is initiated and normal operation resumes.

Holding FSYNC_IN low will disable the IC.

Setting Relative Phase-Shift on CLKOUT

Depending upon the voltage level at PH_CNTRL, set by the VCC

resistor divider output, the ISL8200MMREP operates with

CLKOUT phase shifted, as shown in Table 3. The phase shift is

latched as VCC raises above POR so it cannot be changed

on-the-fly.

Layout Guide

To achieve stable operation, low losses, and good thermal

performance some layout considerations are necessary.

• The ground connection between PGND1 (pin 15) and PGND

(pin 18) should be a solid ground plane under the module.

• Place a high frequency ceramic capacitor between (1) PVIN

and PGND (pin 18) and (2) a 10μF between PVCC and PGND1

(pin 15) as close to the module as possible to minimize high

frequency noise. High frequency ceramic capacitors close to

the module between VOUT and PGND will help to minimize

noise at the output ripple.

• Use large copper areas for power path (PVIN, PGND, VOUT) to

minimize conduction loss and thermal stress. Also, use

multiple vias to connect the power planes in different layers.

• Keep the trace connection to the feedback resistor short.

• Use remote sensed traces to the regulation point to achieve a

tight output voltage regulation, and keep them in parallel.

Route a trace from VSEN_REM- to a location near the load

ground, and a trace from feedback resistor to the point-of-load

where the tight output voltage is desire.

• Avoid routing any sensitive signal traces, such as the VOUT and

VSENREM- sensing point near the PHASE pin.

• FSYNC_IN is a sensitive pin. If it not use for receiving external

synchronization signal, then keep the trace connecting to the

pin short. A bypass capacitor value 100pF connecting between

FSYNC_IN pin and GND1 can help to bypass the noise

sensitivity on the pin.

700

800

900

1000

1100

1200

1300

1400

1500

0

100

200

300

400

RFS-EXT (kΩ)

FIGURE 27. RFS-EXT vs SWITCHING FREQUENCY

TABLE 3.

DECODING

PH_CNTRL RANGE

PHASE FOR CLKOUT WRT

CHANNEL 1

REQUIRED

PH_CNTRL

<29% of VCC

-60°

15% VCC

29% to 45% of VCC

90°

37% VCC

45% to 62% of VCC

120°

53% VCC

62% to VCC

180°

VCC

FIGURE 28. RECOMMENDED LAYOUT

VOUT

PGND

PVIN