HC705MC4GRSSLASHD datasheet(80/180 Pages) NXP

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16-Bit Timer

MC68HC705MC4 — Rev. 2.0

16-Bit Timer

NOTE:

The I bit in the condition code register (CCR) should be set while

manipulating both the high and low byte registers of a specific timer

function. This prevents interrupts from occurring between the time that

the high and low bytes are accessed.

9.3 Timer

The key element of the programmable timer is a 16-bit free-running

counter or timer registers, preceded by a prescaler which divides the

internal clock by four. The prescaler gives the timer a resolution of 1.33

microseconds when a 6 MHz (3 MHz internal bus) crystal is used. The

counter is incremented to increasing values during the low portion of the

internal clock cycle.

NOTE:

Four internal bus cycles must be completed before subsequent access

of TMRH and ACRH. This ensures the timer count has released the

TMRH and ACRH buffers.

The double byte free-running counter can be read from either of two

locations: the timer registers (TMRH, TMRL) or the alternate counter

registers (ACRH, ACRL). Both locations will contain identical values. A

read sequence containing only a read of the LSB of the counter

(TMRL/ACRL) will return the count value at the time of the read. If a read

of the counter accesses the MSB first (TMRH/ACRH) it causes the LSB

(TMRL/ACRL) to be transferred to a buffer. This buffer value remains

fixed after the first MSB byte read even if the MSB is read several times.

The buffer is accessed when reading the counter LSB (TMRL/ACRL),

and thus completes a read sequence of the total counter value. When

reading either the timer or alternate counter registers, if the MSB is read,

the LSB must also be read to complete the read sequence. See Figure

9-2 and Figure 9-3.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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