HC705MC4GRSSLASHD datasheet(97/180 Pages) NXP

97 / 180 page

Pulse Width Modulator

PWM Registers

General Release Specification

Pulse Width Modulator

Figure 10-1. PWM Block Diagram

data register interlock mechanism is managed by mapping each data

(PWMx-D). Writes to the interlock address will engage the interlock

mechanism. Writes to the direct address will not engage the interlock

mechanism unless it is already engaged prior to the write. A write to the

direct address will therefore take immediate effect (if the corresponding

update bit is set) or at the end of the current PWM cycle (if the

corresponding update bit is cleared).

MODULUS &

COMPARATOR B

MODULUS &

COMPARATOR A

BUFFER

8-BIT COUNTER

PWM CONTROL REGISTER B

PWM CONTROL REGISTER A

8-BIT COUNTER

OSC1

RA[2:0]

RA[3]

RB[2:0]

RB[3]

PWM DATA A

BUFFER

PWM DATA B

TO ENABLE

PA1/PWMA1

PA3/PWMA2

PA5/PWMA3

MUX &

CLOCK

GENERATOR

÷ 1.5

CIRCUIT

(6 MHz)

÷ 1.5

CIRCUIT

PA2/PWMB1

PA4/PWMB2

PA6/PWMB3

PORT

LOGIC

MUX &

PORT

LOGIC

ENABLE

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D 数据表(PDF) 97 Page - NXP Semiconductors

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