2

PowerPC 602 RISC Microprocessor Hardware Specifications

1.1 Overview

The 602 is a low-cost, low-power implementation of the PowerPC microprocessor family of reduced

instruction set computing (RISC) microprocessors. The 602 implements the 32-bit portion of the PowerPC

architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-

point data types of 32 and 64 bits. Floating-point operations involving 64-bit data types are not implemented

in the 602. Double-precision floating point operations are trapped for emulation in software.

The 602 provides four software controllable power-saving modes. Three of the modes (the nap, doze, and

sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor.

The fourth is a dynamic power management mode that causes the functional units in the 602 to

automatically enter a low-power mode when the functional units are idle without affecting operational

performance, software execution, or any external hardware.

The 602 is a superscalar processor capable of issuing two instructions (which includes one branch).

Branches are folded out, and the 602 retires one instruction per clock. Instructions can execute out of order

for increased performance; however, the 602 makes completion appear sequential.

The 602 integrates four execution units—an integer unit (IU), a floating-point unit (FPU), a branch

processing unit (BPU), and a load/store unit (LSU). The ability to execute four instructions in parallel and

the use of simple instructions with rapid execution times yield high efficiency and throughput for 602-based

systems. Most integer instructions execute in one clock cycle. The FPU is pipelined so a single-precision

multiply-add instruction can be issued every clock cycle.

The 602 provides independent on-chip, 4-Kbyte, two-way set-associative, physically addressed caches for

instructions and data as well as on-chip instruction and data memory management units (MMUs). The 602

MMUs contain 32-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB

and ITLB). The TLBs and caches use a least recently used (LRU) replacement algorithm. The 602 also

supports block address translation through the use of two independent instruction and data block address

translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously

with all four entries in the BAT array during block translation. If an effective address matches against any

entry in the BATs, the BAT entry takes priority over any potential matches in the TLBs.

The 602 offers an optional configuration (referred to as protection-only mode) of its TLBs under user

control on reset. Applications that do not require address translation through the TLBs can use this

configuration to protect up to 4-Mbytes of memory per TLB. The 602 BATs are available in this optional

configuration for protection and translation of the effective address.

The 602 has a single bus interface used for transferring both 32-bit addresses and 64-bit or 32-bit data. This

bus is time-multiplexed. First the address is driven on the bus, and then the data. During each address phase,

the 602 samples the T32 input pin to determine if the data phase will use a 32-bit bus or a 64-bit bus. The

602 interface protocol allows multiple masters to compete for system resources through a central external

arbiter. The 602 provides a three-state coherency protocol that supports the modified, exclusive, and invalid

(MEI) cache states. This protocol is a compatible subset of the MESI (modified/exclusive/shared/invalid)

four-state protocol and operates coherently in systems that contain four-state caches. The 602 supports

single-beat and burst data transfers for memory accesses and memory-mapped I/O.

The 602 uses an advanced, 3.3-V CMOS process technology and maintains full interface compatibility with

TTL devices.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com