TLK2201A, TLK2201AI

ETHERNET TRANSCEIVERS

SLLS572 – JUNE 2003

4

POST OFFICE BOX 655303

detailed description (continued)

transmission latency

Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of

bit 9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times. The

minimum latency in DDR mode is 29 bit times, and maximum latency in DDR mode is 30 bit times.

10 Bit Code

TXP, TXN

TD(0–9)

REFCLK

td(Tx latency)

10 Bit Code

b9

Figure 1. Transmitter Latency Full Rate Mode

data reception

The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated

clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and

presented to the protocol controller along with receive byte clocks (RBC0, RBC1).

receiver clock select mode

There are two modes of operation for the parallel busses. 1)The 10-bit (TBI) mode and 2) 5-bit (DDR) mode.

When in TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal.

1) Full-rate clock on RBC0 and 2) Half-rate clocks on RBC0 and RBC1. When in the DDR mode, only a full-rate

clock is available on RBC0; refer to Table 1.

Table 1. Mode Selection

MODESEL

RBCMODE

MODE

FREQUENCY

(TLK2201A)

FREQUENCY

(TLK2201AI)

0

0

TBI half-rate

100–125 MHz

120–125 MHz

0

1

TBI full-rate

100–160 MHz

120–160 MHz

1

0

DDR

100–125 MHz

120–125 MHz

1

1

DDR

100–125 MHz

120–125 MHz

In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate

at one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data

is output with respect to the two receive byte clocks (RBC0, RBC1) allowing a protocol device to clock the

parallel bytes using the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received

data valid on the rising edge of RBC1. Refer to the timing diagram shown in Figure 2.