TLK2201A, TLK2201AI

ETHERNET TRANSCEIVERS

SLLS572 – JUNE 2003

9

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

SIGNAL (Continued)

RBCMODE

32

I

P/D†

Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output on

RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on

RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate clock is

output on RBC0 and RBC1 is held low.

SYNCEN

24

I

P/U‡

Synchronous function enable. When SYNCEN is high, the internal synchronization function is activated.

When this function is activated, the transceiver detects the K28.5 comma character (0011111 negative

beginning disparity) in the serial data stream and realigns data on byte boundaries if required. When

SYNCEN is low, serial input data is unframed in RD0 – RD9.

SYNC/PASS

47

O

Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in the serial

data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In PRBS test mode

(PRBSEN=high), SYNC/PASS outputs the status of the PRBS test results (high=pass).

LOS

26

O

Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.

If magnitude of RXP–RXN > 150 mV, LOS = 1, valid input signal

If magnitude of RXP–RXN < 150 mV and > 50 mV, LOS is undefined

If magnitude of RXP–RXN < 50 mV, LOS = 0, loss of signal

MODESEL

15

I

P/D†

Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface. When

low the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected. The default

mode is the TBI.

TEST

LOOPEN

19

I

P/D†

Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted

serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction

with the protocol device. The TXP and TXN outputs are held in a high-impedance state during the

loop-back test. LOOPEN is held low during standard operational state with external serial outputs and

inputs active.

TCK

49

I

Test clock. IEEE1149.1 (JTAG)

JTDI

48

I

P/U‡

Test data input. IEEE1149.1 (JTAG)

JTDO

27

O

Test data output. IEEE1149.1 (JTAG)

JTRSTN

56

I

P/U‡

Reset signal. IEEE1149.1 (JTAG)

JTMS

55

I

P/U‡

Test mode select. IEEE1149.1 (JTAG)

ENABLE

28

I

P/U‡

When this terminal is low, the device is disabled for Iddq testing. RD0 – RD9, RBCn, TXP, and TXN are

high impedance. The pullup and pulldown resistors on any input are disabled. When ENABLE is high, the

device operates normally.

PRBSEN

16

I

P/D†

PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS verification

circuit in the receive side is also enabled. A PRBS signal can be fed to the receive inputs and checked for

errors, that are reported by the SYNC/PASS terminal indicating low.

TESTEN

17

I

P/D†

Manufacturing test terminal

POWER

VDD

5, 10, 20,

23, 29, 37,

42, 50, 63

Supply

Digital logic power. Provides power for all digital circuitry and digital I/O buffers.

VDDA

53, 57, 59,

60

Supply

Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter

VDDPLL

18

Supply

PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.

† P/D = Internal pulldown

‡ P/U = Internal pullup