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TLK2201AI 数据表(PDF) 13 Page - Texas Instruments

部件名 TLK2201AI
功能描述  ETHERNET TRANSCEIVERS
PDF  21 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TLK2201AI 数据表(HTML) 13 Page - Texas Instruments

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TLK2201A, TLK2201AI
ETHERNET TRANSCEIVERS
SLLS572 – JUNE 2003
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
LVTTL output switching characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr(RBC) Clock rise time
0.3
1.5
ns
tf(RBC) Clock fall time
80% to 20% output voltage C
5 pF (see Figure 9)
0.3
1.5
ns
tr
Data rise time
80% to 20% output voltage, C = 5 pF (see Figure 9)
0.3
1.5
ns
tf
Data fall time
0.3
1.5
ns
tsu(D1)
Data setup time (RD0..RD9),
Data valid prior to RBC0 rising
TBI normal mode (see Figure 3)
2.5
ns
th(D1)
Data hold time (RD0..RD9),
Data valid after RBC0 rising
TBI normal mode (see Figure 3)
2
ns
tsu(D2)
Data setup time (RD0..RD4)
DDR mode, R
ω = 125 MHz (see Figure 4)
2
ns
th(D2)
Data hold time (RD0..RD4)
DDR mode, R
ω = 125 MHz (see Figure 4)
0.8
ns
tsu(D3)
Data setup time (RD0..RD9)
TBI half-rate mode, R
ω = 125 MHz (see Figure 2)
2.5
ns
th(D3)
Data hold time (RD0..RD9)
TBI half-rate mode, R
ω = 125 MHz (see Figure 2)
1.5
ns
transmitter timing requirements over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tsu(D4)
Data setup time (TD0..TD9)
TBI modes
1.6
ns
th(D4)
Data hold time (TD0..TD9)
TBI modes
0.8
ns
tsu(D5)
Data setup time (TD0..TD9)
DDR modes
0.7
ns
th(D5)
Data hold time (TD0..TD9)
DDR modes
0.5
ns
tr, tf
TD[0,9] Data rise and fall time
See Figure 9
2
ns
AVAILABLE OPTIONS
PACKAGE
TA
PLASTIC QUAD FLAT PACK
(RCP)
0
°C to 70°C
TLK2201ARCP
– 40
°C to 85°C
TLK2201AIRCP



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