Audio Codec with

ADAV400

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

©2006 Analog Devices, Inc. All rights reserved.

FEATURES

Fully programmable audio digital signal processing (DSP) for

enhanced sound processing

Scalable digital audio delay line

Pool of 400 ms @ 48 kHz (200 ms for stereo channel)

High performance, integrated analog-to-digital converters

(ADCs) and digital-to-analog converters (DACs)

1 stereo analog input (ADC)

4 stereo analog inputs with mux-to-stereo ADC

4 stereo (8-channel) analog outputs (DACs)

Dedicated headphone output with integrated amplifier

Multichannel digital I/O

8- and 16-channel TDM input and output modes

integrated sample rate converter (SRC), supporting

sample rates from 5 kHz to 50 kHz

Features SigmaStudio™, a proprietary graphical

programming tool for fast development of custom

signal flows

Includes various third-party audio algorithms

Operates from 3.3 V (analog), 1.8 V (digital core),

3.3 V (digital interface)

Features on-chip regulator for single 3.3 V operation

80-lead LQFP package (14 mm × 14 mm)

Temperature range: 0°C to 70°C

APPLICATIONS

ATV and AV audio applications

TV audio processing

Set top box (STB)

HTiB

General audio enhancement

FUNCTIONAL BLOCK DIAGRAM

MULTICHANNEL

DIGITAL OUTPUTS

SRC

ASYNCHRONIZE

DIGITAL INPUT

SYNCHRONIZE

MULTICHANNEL

DIGITAL INPUT

PROGRAMMABLE

AUDIO

PROCESSOR

CORE

A–V

SYNC DELAY

MEMORY

PLL

VOUT1

VOUT2

AUXL2

AUXR2

ADAV400

DAC

ADC

HPOUTL

HPOUTR

DAC

AUXL1

AUXR1

LRCLK1

BCLK1

MCLKI

MCLKO

SCL

SDA

AD0

SDIN0

SDIN1

SDIN2

SDIN3

BCLK0

LRCLK0

AINL1

AINR1

AINL4

AINR4

SDO0

SYSTEM

CLOCKS

SDO1

SDO2

SDO3

DAC

VOUT3

VOUT4

DAC

Figure 1.