ADAV400KSTZ datasheet(19/36 Pages) AD

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ADAV400

Rev. 0 | Page 19 of 36

RAMS AND REGISTERS

Table 10. Control Port Addresses

I2C Subaddress

Read/Write Word Length

0 to 1023 (0x0000 to 0x03FF)

Parameter RAM

Write: 4 bytes; read: 4 bytes

1024 to 3584 (0x0400 to 0x0E00)

Program RAM

Write: 6 bytes; read: 6 bytes

4096 to 4159 (0x1000 to 0x103F)

Target/slew RAM

Write: 5 bytes; read: N/A

4160 to 4164 (0x1040 to 0x1044)

Parameter RAM Data Safeload Register [0:4]

Write: 5 bytes; read: N/A

4165 to 4169 (0x1045 to 0x1049)

Parameter RAM Indirect Address Safeload Register [0:4]

Write: 2 bytes; read: N/A

4170 to 4175 (0x104A to 0x104F)

Data Capture Register [0:5] (control port readback)

Write: 2 bytes; read: 3 bytes

4176 to 4177 (0x1050 to 0x1051)

Data capture registers (digital output)

Write: 2 bytes; read: N/A

4178 (0x1052)

Audio core control register

Write: 2 bytes; read: 2 bytes

4179 (0x1053)

RAM modulo control register

Write: 1 byte; read: 1 byte

4180 (0x1054)

Serial output control register

Write: 2 bytes; read: 2 bytes

4181 (0x1055)

Serial input control register

Write: 1 byte; read: 1 byte

4182 (0x1056)

SRC serial port control register

Write: 1 byte; read: 1 byte

4183 (0x1057)

ADC input mux control register

Write: 2 bytes; read: 2 bytes

4184 (0x1058)

Power control register

Write: 2 bytes; read: 2 bytes

4185 (0x1059)

User Control 1 register

Write: 2 bytes; read: 2 bytes

4186 (0x105A)

User Control 2 register

Write: 2 bytes; read: 2 bytes

4365 (0x110D)

DAC amplifier register

Write: 2 bytes; read: 2 bytes

Table 11. RAM Read/Write Modes

Memory

Size

Subaddress Range

Read

Write

Burst Mode Available

Write Modes

Parameter RAM

1024 × 28

0 to 1023

(0x0000 to 0x03FF)

Yes

Direct write,1 safeload write

Program RAM

2560 × 42

1024 to 3584

(0x0400 to 0x0E00)

Yes

Direct write1

Target/Slew RAM

64 × 34

4096 to 4159

(0x1000 to 0x1044)

Yes

Safeload write

1 To avoid clicks or pops, mute the DSP core first.

CONTROL PORT ADDRESSING

Table 10 shows the addressing of the RAM and register spaces

on the ADAV400. The address space encompasses a set of

registers and three RAMs: parameter, program, and target\slew.

Table 11 lists the sizes and available writing modes of the

parameter, program, and target/slew RAMs.

PARAMETER RAM CONTENTS

The parameter RAM is 28 bits wide and occupies Address 0 to

Address 1023. The parameter RAM is initialized to all 0s on

power-up. The data format of the parameter RAM is twos

complement 5.23. This means that the coefficients can range

from +16.0 (−1 LSB) to −16.0, with 1.0 represented by the

binary word 0000 1000 0000 0000 0000 0000 0000.

Options for Parameter Updates

The parameter RAM can be written to and read from using one

of the two following methods:

•

Direct Read/Write.

This method allows direct access to the program and

parameter RAMs. This mode of operation is normally used

during a complete new load of the RAMs using burst mode

addressing. To avoid clicks or pops in the outputs, it is

recommended to set the clear registers bit in the audio core

control register to 0.

•

Safeload Write.

Up to five safeload registers can be loaded with parameter

RAM address data. The data is transferred to the requested

address when the RAM is idle. It is recommended to use

this method for dynamic updates during run time. For

example, a complete update of one biquad section can

occur in one audio frame. This method is not available for

writing to the program RAM or control registers. The

following sections discuss these two options in more detail.

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