ADAV400KSTZ datasheet(13/36 Pages) AD

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ADAV400

Rev. 0 | Page 13 of 36

THEORY OF OPERATION

The ADAV400 is an enhanced audio processor containing an

Analog Devices SigmaDSP digital processing core. The core can

accept up to four digital stereo channels, typically at 48 kHz, or

three channels, typically at 48 kHz, and one channel at any

sample rate between 5 kHz and 50 kHz. In addition, up to four

stereo analog inputs can be used as the source for the DSP core

using the stereo ADC and a four-stereo input mux.

Outputs from the DSP core are available as four stereo digital

outputs and four stereo analog outputs.

The core of the ADAV400 is a 28-bit DSP (56-bit with double

precision) optimized for audio processing. Signal processing

parameters are stored in a 1024-location parameter RAM. The

program RAM can be loaded with a custom program after

power-up. New values are written to the program and parameter

RAM using the I2C control port. The values stored in the

parameter RAM control individual signal processing blocks,

such as IIR equalization filters, dynamics processors, audio

delays, and mixer levels. A safeload feature allows transparent

updating of these parameters, eliminating the risk of unwanted

pops or clicks on the outputs.

The ADAV400 has a sophisticated control port that supports

complete read/write capability of all memory locations except

the target/slew RAM and data RAM, which are only accessible

by the DSP core.

The ADAV400 has a very flexible serial data input and output

port that allows for glueless interconnection to a variety of

ADCs, DACs, general-purpose DSPs, S/PDIF receivers, and

sample rate converters. The digital inputs and outputs of the

ADAV400 can be configured in I2S, left-justified, right-justified,

or TDM serial port-compatible mode. They can support 16, 20,

or 24 bits in all modes. The ADAV400 accepts serial audio data

in MSB-first and twos complement formats.

The digital core of the ADAV400 operates at 1.8 V, and the

other circuit blocks operate from a 3.3 V power supply. An on-

board regulator allows a single 3.3 V supply for both digital

supplies using the configuration shown in Figure 19.

The ADAV400 is fabricated on a single monolithic integrated

circuit and is housed in an 80-lead LQFP package for operation

over the 0°C to 70°C consumer temperature range.

ANALOG INPUTS

The ADAV400 has four stereo analog inputs. An input

multiplexer is included that enables any of these four stereo

analog inputs to be connected to the ADC. The analog inputs

are current input, see Figure 17 for the suggested input

configuration when the required input level is 2 V rms.

AINLx

20kΩ

47µF

20kΩ

AINRx

IDAC

Figure 17. Analog Input Configuration

SAMPLE RATE CONVERTER BLOCK

The ADAV400 contains a stereo SRC that accepts input sample

rates in the range of 5 kHz to 50 kHz. Any one of the digital

inputs can be selected as the source for the SRC.

Note that the SRC has a filter cutoff frequency of 20 kHz for a

48 kHz sample rate. If a different input sample rate is used, the

cutoff frequency scales accordingly.

PLL BLOCK

The ADAV400 contains a phase-locked loop (PLL) that

generates all of the internal clocks required by the ADAV400.

The master clock frequency can be 64 × fS, 128 × fS, 256 × fS, or

512 × fS.

The PLL requires some external components to operate

correctly, as shown in Figure 18. These components form a loop

filter that integrates pulses from a charge pump and produces a

voltage to tune the VCO. Internally the PLL can generate clocks

up to 200 MHz, so it is recommended that a suitable capacitor is

selected.

PLL

BLOCK

AVDD2

PLL_LF

100nF

1nF

2kΩ

Figure 18. PLL Loop Filter Components

A 3.3 V analog supply connected to AVDD2 is required to

operate the PLL. Where the supply for AVDD1 is also used for

the PLL, additional filtering is recommended to prevent digital

noise created by the PLL block being coupled to the analog

circuitry powered by the AVDD1 supply.

ANALOG OUTPUTS

The ADAV400 contains four stereo analog outputs typically at

1 V rms. One stereo pair of DACs is connected to integrated

headphone amplifiers HPOUTL and HPOUTR, but is also

available on the AUXL1 and AUXR1 pins.

Note that the outputs of all the DACs are inverted with the

exception of the headphone channel. If required, this can be

changed using the invert library block of the DSP.

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