ADAV400

Rev. 0 | Page 10 of 36

Pin No.

Mnemonic

I/O

Description

33

MCLKI

I

Master Clock Input. The ADAV400 uses a phase-locked loop (PLL) to generate all of the appropriate

internal clock for the DSP core.

34

MCLKO

O

Audio Clock Output. The MCLKO pin can be programmed to output the internal audio clock.

35

BCLK1

I/O

Bit Clock for Serial Data Input/Output. This clock and the LRCLK1 are used as clock and frame sync signals

for the SDINx and SDOx pins. These clocks are inputs to the ADAV400 when the port is configured as a

slave, and outputs when the port is configured as a master. On power up, these pins are set to slave mode

to avoid conflicts with external master mode devices.

36

LRCLK1

I/O

Left/Right Clock for Serial Data Input/Output. This clock and the BCLK1 are used as clock and frame sync

signals for the SDINx and SDOx pins.

37, 38,

42, 43

SDO [0:3]

0

Serial Data Outputs.

39, 44,

45

NC

These pins should be left unconnected.

46

RESET

I

Active Low Reset Signal. After RESET the ADAV400 is powered down.

49

AVDD2

Analog Power Supply Pin for the PLL. Connect this pin to 3.3 V and decouple to AGND (Pin 51).

50

PLL_LF

PLL Loop Filter. External components are required to allow the PLL to function correctly. See the PLL

Block section for details of these components.

51

AGND

PLL Ground. Connect this pin to the analog ground plane.

52

AGND

Headphone Driver Ground. Connect this pin to the analog ground plane.

53

HPOUTL

O

Left Headphone Output. Analog output from the headphone amplifiers.

54

HPOUTR

O

Right Headphone Output. Analog output from the headphone amplifiers.

55

AVDD3

Analog Power Supply Pin for the headphone amplifier. Connect this pin to 3.3 V and decouple to AGND

(Pin 52).

56

AUXL1

O

Auxiliary Analog Output Left 1

57

AUXR1

O

Auxiliary Analog Output Right 1.

58 to 61

VOUT [1:4]

O

Main Analog Output 1 to Output 4.

62

AUXL2

O

Auxiliary Analog Output Left 2.

63

AUXR2

O

Auxiliary Analog Output Right 2.

64

TEST2

Test Pin. This pin should be left unconnected.

67

FILTD

DAC Filter Decoupling Node. Decouple this pin to AGND (Pin 69).

68

AVDD4

Analog Power Supply Pin for the DAC. Connect this pin to 3.3 V and decouple to AGND (Pin 69).

69, 70

AGND

DAC Ground. Connect this pin to the analog ground plane.

71

AVDD5

Analog Power Supply Pin for the DAC. Connect this pin to 3.3 V and decouple to AGND (Pin 70).

72, 74,

76, 78

AINL [1:4]

I

Left Analog Input 1 to Input 4. The analog inputs are current inputs typically driven via a 20 kΩ resistor for

2 V rms input, as shown in Figure 17.

73, 75,

77, 79

AINR [1:4]

I

Right Analog Input 1 to Input 4. The analog inputs are current inputs typically driven via a 20 kΩ resistor

for 2 V rms input, as shown in Figure 17.

80

IDAC

DAC External Bias Resistor. This is an external bias pin for the DAC circuitry. Connect a 20 kΩ resistor

between this pin and AGND.