ADL5310

Rev. A | Page 5 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24

1

2

3

4

5

6

18

17

16

15

14

13

23

22

21

20

19

7

8

9

10

11

12

PIN 1

INDICATOR

TOP VIEW

(Not to Scale)

ADL5310

DUAL LOG AMP

VSUM

INP1

IRF1

IRF2

INP2

VSUM

SCL1

BIN1

LOG1

LOG2

BIN2

SCL2

Figure 2. 24-Lead LFCSP Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Function

1, 6

VSUM

Guard Pin. Used to shield the INP1 and INP2 input current lines, and for optional adjustment of the input

summing node potentials. Pin 1 and Pin 6 are internally shorted.

2

INP1

such that photocurrent flows into INP1.

3

IRF1

4

IRF2

5

INP2

such that photocurrent flows into INP2.

7, 24

VREF

Reference Output Voltage of 2.5 V. Pin 7 and Pin 24 are internally shorted.

8, 9

VPOS

10, 11, 20

VNEG

Applications sections. All VNEG pins must be connected externally.

12

OUT2

Buffer Output for Channel 2.

13

SCL2

Buffer Amplifier Inverting Input for Channel 2.

14

BIN2

Buffer Amplifier Noninverting Input for Channel 2.

15

LOG2

Output of the Logarithmic Front End for Channel 2.

16

LOG1

Output of the Logarithmic Front End for Channel 1.

17

BIN1

Buffer Amplifier Noninverting Input for Channel 1.

18

SCL1

Buffer Amplifier Inverting Input for Channel 1.

19

OUT1

Buffer Output for Channel 1.

21, 22

COMM

Analog Ground. Pin 21 and Pin 22 are internally shorted.

23

VRDZ

Intercept Shift Reference Input. The top of a resistive divider network that offsets VLOG to position the

intercept. Normally connected to VREF; may also be connected to ground when bipolar outputs are to be

provided.