ICS527-04

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

PECL ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

3

ICS527-04

REV F 051310

External Components

Decoupling Capacitors

The ICS527-04 requires two 0.01

µF decoupling

capacitors to be connected between VDD and GND,

one on each side of the chip. They must be connected

close to the device to minimize lead inductance. The

output levels can be adjusted for different output and

load impedances. Refer to application note MAN09 for

more information on the RES and resistor network

values for the output clocks.

PECL Termination Networks

The PECLO to FBPECL and PECLO to FBPECL

connections should be made directly underneath the

device, unless feedback is being routed through other

devices. The resistor divider networks should be placed

as close to the outputs as possible.

Typical 50

Ω termination is shown in the Block Diagram

on page 1. For other termination schemes, see

MAN09.pdf.

Eliminating the Delay Through Buffers or

Other Components

More complicated feedback schemes can be used,

such as incorporating low skew, multiple output buffers

in the feedback path. An example of this is given later in

the datasheet. The fundamental property of the

ICS527-04 is that it aligns rising edges on CLKIN and

FBPECL at a ratio determined by the reference and

feedback dividers. This means that any delay in the

feedback path will cause the PECL output edge to lead

PECLIN by the delay amount. So, by taking the PECL

output from another device as the input to FBPECL, the

delay through the other device can be eliminated.

Setting the Clock Slicer

Use IRANGE to select the input frequency range. If

either the PECLIN or FBPECL pair frequencies are

greater than (or equal to) 80 MHz, connect IRANGE to

VDD, or let it float. If both frequencies are less than 80

MHz, connect IRANGE to ground.

Choose S1 and S0 from the table on page 2, depending

on the output frequency.

Finally, the divider settings should be selected.

Following is a description of how the dividers should be

set.

Determining ICS527-04 Divider Settings

The user has full control in setting the desired output

clock over the range shown in the table on page 2. The

user should connect the divider select input pins directly

to ground (or VDD, although this is not required

because of internal pull-ups) during Printed Circuit

Board layout, so that the ICS527-04 automatically

produces the correct clock when all components are

soldered. It is also possible to connect the inputs to

parallel I/O ports in order to switch frequencies. The

configuration inputs: IRANGE, S1, S0, R6...0, F6...0 are

compatible with CMOS or TTL levels.

The output of the ICS527-04 can be determined by the

following simple equation:

Where:

Reference Divider Word (RDW) = 0 to 127

Feedback Divider Word (FDW) = 0 to 127

FB Frequency is the same as the output

frequency

Additionally, the following operating ranges should be

observed:

S1 and S0 should be selected depending on the

output frequency. The table on page 2 gives the

ranges.

The dividers are expressed as integers. For example, if

a 50 MHz output on CLK1 is desired from a 40 MHz

input, the reference divider word (RDW) should be 2

and the feedback divider word (FDW) should be 3 which

gives the required 5/4 multiplication. If multiple choices

FB Frequency

Input Frequency

FDW

2

+

RDW

2

+

------------------------

×

=

300kHz

Input Frequency

RDW

2

+

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