ICS527-04

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

PECL ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

6

ICS527-04

REV F 051310

PCB Layout Recommendations

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

1) Each 0.01µF decoupling capacitor should be

mounted on the component side of the board as close

to the VDD pin as possible. No via’s should be used

between decoupling capacitor and VDD pin. The PCB

trace to VDD pin should be kept as short as possible, as

should the PCB trace to the ground via.

2) PECL termination networks should be located as

close to the outputs as possible.

3) An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers. Other signal traces should be routed away

from the ICS527-04. This includes signal traces just

underneath the device, or on layers adjacent to the

ground plane layer used by the device.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS527-04. These ratings,

which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of

the device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical parameters are guaranteed only over the recommended operating

temperature range.

Recommended Operation Conditions

Item

Rating

Supply Voltage, VDD

7 V

All Inputs and Outputs

-0.5 V to VDD+0.5 V

Ambient Operating Temperature

0 to +70

° C

Storage Temperature

-65 to +150

° C

Junction Temperature

125

° C

Soldering Temperature

260

° C

Parameter

Min.

Typ.

Max.

Units

Ambient Operating Temperature

0

+70

° C

Power Supply Voltage (measured in respect to GND)

+3.15

+3.3

+3.45

V