ICS527-04

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

PECL ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

5

ICS527-04

REV F 051310

Multiple Output Example

In this example, an input clock of 125 MHz is used. Four low skew copies of 50 MHz PECL are required

aligned to the 125 MHz input clock. The following solution uses the ICS554-01A, which is a 1 to 4 PECL

buffer with low pin to pin skew.

Using the equation for selecting dividers gives:

If FDW = 0, then RDW = 3. This gives the required divide-by-5 function. Setting pin IRANGE = 1 (by leaving

it unconnected and using the internal pull-up) allows a higher speed input clock like the 125 MHz. The

FBPECL pair pins are connected to the Q1 outputs (chosen arbitrarily) of the ICS554. This aligns all the

outputs of the ICS554 with the 125 MHz input since the ICS527-04 aligns rising edges on the PECLIN and

FBPECL pins.

In this example, the resistor network needed for each PECLO output is represented by the

boxes.

125 MHz, PECLIN

50 MHz, PECLO

(Complementary outputs are not shown)

F6

FBPECL

F5

F4

GND

F3

PECLIN

PECLIN

F0

F1

F2

PECLO

PECLO

GND

S1

VDD

R0

VDD

IRANGE

S0

R2

R1

R5

R6

R4

R3

FBPECL

RES

0.01 F

0.01 F

VDD

Q2

Q0

GND

Q1

GND

Q2

Q0

VDD

VDD

OE

NC

Q1

0.01 F

The layout design above produces the waveforms shown below.

RN

50 MHz

125 MHz

RN

IN

IN

Q3

Q3

RN

RN

RN

RN

RN

RN

RN

RN

560

0.01 F

125 MHz

50 MHz = 125 MHz *

(FDW + 2)

(RDW + 2)

RN