DATASHEET

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

ICS527-04

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

1

ICS527-04

REV F 051310

Description

The ICS527-04 Clock Slicer is the most flexible way to

generate an output clock from an input clock with zero

skew. The user can easily configure the device to

produce nearly any output clock that is multiplied or

divided from the input clock. The part supports

non-integer multiplications and divisions. Using

Phase-Locked Loop (PLL) techniques, the device

accepts an input clock up to 200 MHz and produces an

output clock up to 160 MHz.

The ICS527-04 aligns rising edges on PECLIN with

FBPECL at a ratio determined by the reference and

feedback dividers.

For other PECL output clocks, see the ICS507-01,

ICS525-03, or the MK3707. For PECL in and CMOS

out, see the ICS527-02. For CMOS in and PECL out

with zero delay, use the ICS527-03.

Features

• Packaged as 28-pin SSOP (150 mil body)

• Synchronizes fractional clocks rising edges

• CMOS in to PECL out

• PECL in to PECL out

• Pin selectable dividers

• Zero input to output skew

• User determines the output frequency - no software

needed

• Slices frequency or period

• Input clock frequency of 1.5 MHz - 200 MHz

• Output clock frequencies up to 160 MHz

• Very low jitter

• Duty cycle of 45/55

• Operating voltage of 3.3 V

• Advanced, low power CMOS process

Block Diagram

PECLIN

VDD

GND

2

2

PECLO

Reference

Divider

PECLIN

Phase Comparator,

Charge Pump, and

Loop Filter

VCO

Output

Divider

7

7

R6:R0

F6:F0

S1:S0

Feedback

Divider

1

0

Divide

by 2

FBPECL

FBPECL

1

0

Divide

by 2

VDD

RES

IRANGE

560 ohm

68 ohm

180 ohm

68 ohm

180 ohm

2

PECLO

VDD

VDD