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ADCMP606 数据表(PDF) 11 Page - Analog Devices |
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ADCMP606 数据表(HTML) 11 Page - Analog Devices |
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11 / 16 page ![]() Preliminary Technical Data ADCMP606/ADCMP607 Rev. PrA | Page 11 of 16 CROSSOVER BIAS POINT maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 18 illustrates the amount of hysteresis applied as a function of the external resistor value, and Figure TBD illustrates hysteresis as a function of the current. In both op amps and comparators, rail-to-rail inputs of this type have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some predeter- mined point in the common-mode range, a crossover occurs. At this point, normally V The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 7k ± 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the HYS pin because it impairs the latch function and often degrades the jitter performance of the device. As described in the CC /2, the direction of the bias current reverses and the measured offset voltages and currents change. The ADCMP606/ADCMP607 slightly elaborate on this scheme. With VCC less than 4 V, this crossover is at the expected VCC/2, but with VCC greater than 4 V, the crossover point instead follows VCC 1:1, bringing it to approximately 3 V with VCC at 5 V. This means that at any voltage, the comparator input characteristics more closely resemble the inputs of nonrail-to-rail ground sensing comparators, such as the AD8611. Using/Disabling the Latch Feature section, hysteresis control need not compromise the latch function. MINIMUM INPUT SLEW RATE REQUIREMENT (Remove if device is stable.) As with most high speed comparators without hysteresis, a minimum slew rate must be met to ensure that the device does not oscillate as the input signal crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator in combination with feedback parasitics inherent in the package and PC board. A minimum slew rate of TBD V/μs ensures clean output transitions from the ADCMP606/ADCMP607 comparators unless hysteresis is programmed. In many applications, chattering due to the absence of hysteresis is not harmful. Figure 18. Hysteresis vs. R Control Resistor HYS |
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