Preliminary Technical Data

ADCMP606/ADCMP607

Rev. PrA | Page 13 of 16

TIMING INFORMATION

Figure 26 illustrates the ADCMP606/ADCMP607 timing relationships. Table 6 provides definitions of the terms shown in the figure.

1.1V

50%

DIFFERENTIAL

INPUT VOLTAGE

LATCH ENABLE

Q OUTPUT

50%

Q OUTPUT

Figure 26. System Timing Diagram

Table 6. Timing Descriptions

Symbol

Timing

Description

t

Input to output high delay

Propagation delay measured from the time the input signal crosses the reference (± the

input offset voltage) to the 50% point of an output low-to-high transition.

PDH

t

Input to output low delay

Propagation delay measured from the time the input signal crosses the reference (± the

input offset voltage) to the 50% point of an output high-to-low transition.

PDL

t

Output rise time

Amount of time required to transition from a low to a high output as measured at the 20%

and 80% points.

R

t

Output fall time

Amount of time required to transition from a high to a low output as measured at the 20%

and 80% points.

F

V

Voltage overdrive

Difference between the input voltages V

OD

A

and V .

B