CS5421

http://onsemi.com

13

C per watt).

manufacturer’s data sheets. Its value is dependent on the

mold compound and lead frames used in assembly of the

semiconductor device in question.

to the heatsink. This component of the thermal resistance is

dependent on the roughness of the heatsink and component

be reduced by using thermal pads or by applying a thin layer

of thermal grease between the case and the heatsink. Such

materials reduce the air gap normally found between the

heatsink and the case and provide a better path for thermal

manufacturers of heatsinks and thermal compounds.

increased power dissipation without exceeding the

maximum junction temperature of the component. Values of

manufacturers.

The basic equation for selecting a heatsink is:

P +

TJ * TA

QJC ) QCS ) QSA

where:

C per watt);

per watt);

C per watt).

required to keep the calculated junction temperature at the

given level of power dissipation below the component

manufacturer’s maximum junction temperature.

EMI MANAGEMENT

As a consequence of large currents being turned on and off

at high frequency, switching regulators generate noise as a

consequence of their normal operation. When designing for

compliance with EMI/EMC regulations, additional

components may be added to reduce noise emissions. These

components are not required for regulator operation and

experimental results may allow them to be eliminated. The

input filter inductor may not be required because bulk filter

and bypass capacitors, as well as other loads located on the

board will tend to reduce regulator di/dt effects on the circuit

board and input power supply. Placement of the power

component to minimize routing distance will also help to

reduce emissions.

LAYOUT GUIDELINES

When laying out the CPU buck regulator on a printed

circuit board, the following checklist should be used to

ensure proper operation of the CS5421.

1. Rapid changes in voltage across parasitic capacitors

and abrupt changes in current in parasitic inductors

are major concerns for a good layout.

2. Keep high currents out of sensitive ground

connections.

3. Avoid ground loops as they pick up noise. Use star or

single point grounding.

4. For high power buck regulators on double−sided

PCB’s a single ground plane (usually the bottom) is

recommended.

5. Even though double sided PCB’s are usually

sufficient for a good layout, four−layer PCB’s are the

optimum approach to reducing susceptibility to

noise. Use the two internal layers as the power and

GND planes, the top layer for power connections and

component vias, and the bottom layers for the noise

sensitive traces.

6. Keep the inductor switching node small by placing

the output inductor, switching and synchronous FETs

close together.

7. The MOSFET gate traces to the IC must be short,

straight, and wide as possible.

8. Use fewer, but larger output capacitors, keep the

capacitors clustered, and use multiple layer traces

with heavy copper to keep the parasitic resistance

low.

9. Place the switching MOSFET as close to the +5.0 V

input capacitors as possible.

10. Place the output capacitors as close to the load as

possible.

11. Place the COMP capacitor as close as possible to the

COMP pin.

12. Connect the filter components of the following pins:

trace, and connect this local GND trace to the output

capacitor GND.

to the IC.