CS5421 datasheet(4/14 Pages) ONSEMI

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CS5421

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ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 μF,

10.8 V < VCC < 13.2 V; CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF, unless otherwise specified.)

Characteristic

Unit

Max

Typ

Min

Test Conditions

PWM Comparator

Transient Response

COMP1,2 = 1.0 V, VFB1(2) = VFFB1(2) = 0 to 1.2 V

−

150

300

PWM Comparator Offset

VFFB1(2) = 0 V; Increase COMP1,2 until

GATE(H)1,2 starts switching

0.30

0.45

0.60

Artificial Ramp

Duty cycle = 50%, Note 3

100

VFFB1(2) Bias Current

VFFB1(2) = 0 V

−

0.4

1.5

μA

VFFB1(2) Input Range

−

0.0

−

1.1

Minimum Pulse Width

−

300

Oscillator

Switching Frequency

ROSC = 61.9 k; Measure GATE(H)2, Note 3

112

150

188

kHz

Switching Frequency

ROSC = 30.9 k; Measure GATE(H)2

224

300

376

kHz

Switching Frequency

ROSC = 11.8 k; Measure GATE(H)2, Note 3

600

750

900

kHz

ROSC Voltage

ROSC = 30.9 k, Note 3

0.970

1.000

1.030

Phase Difference

−

180

−

Supply Currents

VCC Current

COMP1,2 = 0 V (No Switching)

−

SGND Current

−

150

225

μA

Undervoltage Lockout

Start Threshold

GATE(H) Switching; COMP1,2 charging

7.8

8.6

9.6

Stop Threshold

GATE(H) not switching; COMP1,2 discharging

7.0

7.8

8.6

Hysteresis

Start−Stop

0.5

0.8

1.5

3. Guaranteed by design, not 100% tested in production.

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

PIN SYMBOL

FUNCTION

16 Lead SO Narrow

GATE(H)1

High Side Switch FET driver pin for the channel 1 FET.

GATE(L)1

Low Side Synchronous FET driver pin for the channel 1 FET.

PGND1

High Current ground for the GATE(H)1 and GATE(L)1 pins.

LGND

Logic ground. All control circuits are referenced to this pin. IC

substrate connection.

SGND

Ground sense for the internal reference.

VFFB1

Input for the channel 1 PWM comparator.

VFB1

Error amplifier inverting input for channel 1.

COMP1

Channel 1 Error Amp output. PWM Comparator reference

input. A capacitor to LGND provides Error Amp compensa-

tion. The same capacitor provides Soft Start timing for chan-

nel 1. This pin also disables the channel 1 output when

pulled below 0.3 V.

COMP2

Channel 2 Error Amp output. PWM Comparator reference

input. A capacitor to LGND provides Error Amp compensa-

tion and Soft Start timing for channel 2. Channel 2 output is

disabled when this pin is pulled below 0.3 V.

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