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74LVC595A 数据表(PDF) 1 Page - Nexperia B.V. All rights reserved |
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74LVC595A 数据表(HTML) 1 Page - Nexperia B.V. All rights reserved |
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1 / 18 page ![]() 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 3 — 19 November 2021 Product data sheet 1. General description The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 1.2 V to 3.6 V • Overvoltage tolerant inputs to 5.5 V • CMOS low power dissipation • Direct interface with TTL levels • IOFF circuitry provides partial Power-down mode operation • Balanced propagation delays • All inputs have Schmitt-trigger action • Complies with JEDEC standard: • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Applications • Serial-to-parallel data conversion • Remote control holding register |
类似零件编号 - 74LVC595A |
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类似说明 - 74LVC595A |
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