Nexperia

74LVC595A

8-bit serial-in/serial-out or parallel-out shift register; 3-state

mna558

STCP input

Qn output

tPLH

tPHL

tW

tsu

1/fmax

VM

VOH

VI

GND

VOL

VM

SHCP input

VI

GND

VM

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig. 8. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width

and the shift clock to storage clock set-up time

mna560

GND

GND

th

tsu

th

tsu

VM

VM

VM

VI

VOH

VOL

VI

Q7S output

SHCP input

DS input

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig. 9. The data set-up and hold times for the serial data input (DS)

001aaf571

MR input

STCP input

Qn outputs

tsu

VM

VI

VI

GND

GND

VOH

VOL

VM

VM

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig. 10. The master reset (MR) to storage clock (STCP) set-up times

74LVC595A

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Product data sheet

Rev. 3 — 19 November 2021

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