Data Sheet

ADRF5054

THEORY OF OPERATION

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Rev. 0 | 10 of 13

The ADRF5054 can interface CMOS-/LVTTL-compatible logic di-

rectly. The V1 and V2 pins determine which RF port is in the

insertion loss state and in the isolation state. See Table 7 for the

control voltage truth table.

RF INPUT AND OUTPUT

The RF ports (RFC, RF1 to RF4) are DC-coupled to 0 V, and no

DC blocking is required at the RF ports when the RF line potential

is equal to 0 V. The RF ports are internally matched to 50 Ω.

The ADRF5054 is bidirectional with equal power handling capabili-

ties. The RF input signal can be applied to the RFC port or the

selected RF throw port.

The insertion loss path conducts the RF signal between the select-

ed RF throw port and the RF common port. The isolation paths

provide high loss between the insertion loss path and the unselect-

ed RF throw ports. The unselected RF ports of the ADRF5054 are

reflective.

The power handling of the ADRF5054 derates with frequencies less

than 3 GHz. See Figure 2 for the derating of the RF power toward

the lower frequencies.

POWER SUPPLY

The ADRF5054 requires a positive supply voltage applied to the

VDD pin, and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

minimize RF coupling.

The ideal power-up sequence is as follows:

1. Connect GND.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp-up.

3. Apply digital control inputs. The relative order of the control

inputs is not important. However, powering the digital control

inputs before the VDD supply can inadvertently forward bias

and damage the internal ESD protection structures. To avoid

this damage, use a series 1 kΩ resistor to limit the current

flowing into the control pin. Use pull-up or pull-down resistors if

the controller is in a high impedance state after VDD is powered

up and the control pins are not driven to a valid logic state.

4. Apply the RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.

Table 7. Control Voltage Truth Table

Digital Control Inputs

RFx Paths

V1

V2

RFC to RF1

RFC to RF2

RFC to RF3

RFC to RF4

Low

Low

Insertion loss (on)

Isolation (off)

Isolation (off)

Isolation (off)

High

Low

Isolation (off)

Insertion loss (on)

Isolation (off)

Isolation (off)

Low

High

Isolation (off)

Isolation (off)

Insertion loss (on)

Isolation (off)

High

High

Isolation (off)

Isolation (off)

Isolation (off)

Insertion loss (on)